US 8,013,361 B2Granted

Semiconductor device and method for fabricating the same

AssigneePanasonic Corporation

InventorsKyoji Yamashita, Katsuhiro Otani, Katsuya Arai, Daisaku Ikoma

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Abstract

Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a first-level interconnect M1H, and the gate electrode 5E and N-type impurity diffusion regions 7A6 are connected through a shared contact 9A2 to a first-level interconnect M1I. In this way, contact pad parts of the gate electrodes 5A through 5F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.

Claims12

Dependent claims

A semiconductor device comprising:

an isolation insulating film formed in a substrate;
a first region in the substrate surrounded by the isolation insulating film;
a second region in the substrate surrounded by the isolation insulating film and arranged with the isolation insulating film sandwiched between the first and second regions;
a first gate electrode extending across the first region and the isolation insulating film onto the second region;
a well of a first conductivity type having an upper portion including a lower portion of the first region, a lower portion of the second region, and a lower portion of the isolation insulating film formed between the first and second regions;
first impurity diffusion regions of the second conductivity type located to both sides of the first gate electrode of the first region and formed in direct contact with the well of the first conductivity type;
second impurity diffusion regions of the first conductivity type located to both sides of the first gate electrode of the second region and formed in direct contact with the well of the first conductivity type;
a shared contact passing through an interlayer insulating film formed on the substrate and connected to the first gate electrode and the second impurity diffusion region;
and
an interconnect formed on the interlayer insulating film and connected to the shared contact.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/270,602Filed 10 Nov 2005
Priority: JP 2004-32684010 Nov 2004
Published: US 2006/0097294 A111 May 2006
Granted: 6 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 64/519
Characterised by the conducting layers: characterised by their top-view geometrical layouts
H10D 84/0133
Manufacturing their source or drain regions, e.g. silicided source or drain regions: manufacturing common source or drain regions between multiple…
H10D 84/0149
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes