Semiconductor device having a junction of P type pillar region and N type pillar region

A semiconductor device comprising:

• a first semiconductor layer of a first conductivity type;
• a first semiconductor pillar region of the first conductivity type provided on a major surface of the first semiconductor layer;
• a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the first semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the first semiconductor layer together with the first semiconductor pillar region;
• a first main electrode provided on a side opposite to the major surface of the first semiconductor layer;
• a first semiconductor region of the second conductivity type selectively provided on the first semiconductor pillar region and the second semiconductor pillar region;
• a second semiconductor region of the first conductivity type selectively provided in a surface of the first semiconductor region;
• a second main electrode provided in contact with the first semiconductor region and the second semiconductor region;
• a control electrode provided on the first semiconductor region, the second semiconductor region, and the first semiconductor pillar region via an insulating film;
• a second semiconductor layer of the first conductivity type provided on the first semiconductor layer in an edge termination section outside a device section including the periodic arrangement structure of the first semiconductor pillar region and the second semiconductor pillar region, the second semiconductor layer having a lower dopant concentration than the first semiconductor pillar region;
• a guard ring layer of the second conductivity type semiconductor selectively buried in a surface of the second semiconductor layer in the edge termination section;
• and
• a buried guard ring layer of the second conductivity type semiconductor selectively buried in the second semiconductor layer, the buried guard ring layer being a low-dopant concentrated layer which is depleted upon application of high voltage, the buried guard ring layer provided in contact with an outer corner on the edge termination section side of a bottom of an outermost region in the first semiconductor region.