Double-sided integrated circuit chips

A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:

• one or more first devices of a first substrate, said first substrate comprising a first oxide layer, a first silicon layer on said first oxide layer and a first lowermost dielectric layer on said first silicon layer;
• one or more second devices of a second substrate, said second substrate comprising a second oxide layer, a second silicon layer on said second oxide layer and a second lowermost dielectric layer on said second silicon layer;
• an inter-substrate dielectric layer on top of said first oxide layer,
• electrically conductive landing pads in said inter-substrate dielectric layer, said landing pads extending from a top surface of said inter-substrate dielectric layer completely through said inter-substrate dielectric layer and through said first oxide layer to source/drains of said first devices in said first silicon layer;
• a silicon oxide bonding layer on top of said inter-substrate dielectric layer, an entire top surface of said bonding layer bonded to an entire top surface of said second oxide layer;
• electrically conductive first contacts extending from a top surface of said first lowermost dielectric layer through said first lowermost dielectric layer to said first devices;
• electrically conductive second contacts extending from said top surface of said second lowermost dielectric layer through said second lowermost dielectric layer, through said second oxide layer, through said silicon bonding layer to said landing pads;
• and
• one or more second wiring levels over said second lowermost dielectric layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said second contacts.