Nonvolatile storage device and method for manufacturing same
AssigneeKabushiki Kaisha Toshiba
InventorMasahiro Kiyotoshi
Life of this patent
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Abstract
A nonvolatile storage device having a plurality of unit memory layers, and a plurality of layer selection transistors is provided. The plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers. Each of the unit memory layers includes a plurality of first wirings, a plurality of second wirings provided non-parallel to the plurality of first wirings, and a recording layer provided between the plurality of first wirings and the plurality of second wirings. The plurality of layer selection transistors are connected to at least one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, and collectively selects the at least one in the same plane.
Claims19
A nonvolatile storage device comprising:
- a plurality of unit memory layers;
- and
- a plurality of layer selection transistors,
- wherein the plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers,
- wherein each of the unit memory layers includes:
- a plurality of first wirings,
- a plurality of second wirings provided non-parallel to the plurality of first wirings, and
- a recording layer provided between the plurality of first wirings and the plurality of second wirings,
- wherein each of the plurality of layer selection transistors is connected to each of one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers,
- wherein the plurality of layer selection transistors are configured to collectively select some of the one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, the selected some being disposed in a common plane, and
- wherein the layer selection transistors include a channel along a direction perpendicular to the layer surface of the unit memory layers, and can collectively select the some in a plane perpendicular or parallel to the layer surface.
A nonvolatile storage device comprising:
- a plurality of unit memory layers;
- and
- a plurality of layer selection transistors,
- wherein the plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers,
- wherein each of the unit memory layers includes:
- a plurality of first wirings,
- a plurality of second wirings provided non-parallel to the plurality of first wirings, and
- a recording layer provided between the plurality of first wirings and the plurality of second wirings,
- wherein each of the plurality of layer selection transistors is connected to each of one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers,
- wherein the plurality of layer selection transistors is configured to collectively select some of the one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, the selected some being disposed in a common plane, and
- wherein the layer selection transistors include a channel along a direction parallel to the layer surface of the unit memory layer, include a silicon layer provided via an insulating layer on a semiconductor substrate, and can collectively select the some in a plane perpendicular or parallel to the layer surface.
A method for manufacturing a nonvolatile storage device, the nonvolatile storage device including a plurality of unit memory layers laminated in a direction perpendicular to a layer surface of the plurality of unit memory layers, and each of the plurality of unit memory layers including a first wiring, a second wiring provided non-parallel to the first wiring, and a recording layer provided between the first wiring and the second wiring;
- comprising:
- forming a plurality of layer selection transistors on a semiconductor substrate;
- forming the unit memory layers;
- and
- connecting one of the first wirings and the second wirings in each layer in the unit memory layers to the layer selection transistors, respectively,
- the forming the plurality of layer selection transistors including forming a channel of the layer selection transistor, the channel being along a direction perpendicular to the layer surface of the unit memory layers, and
- the plurality of layer selection transistors being able to collectively select the some in a plane perpendicular or parallel to the layer surface.
Dependencies are inferred from the claim text.