Semiconductor chip substrate with multi-capacitor footprint
AssigneeATI Technologies ULC
InventorsYue Li, Silqun Leung, Terence Cheung, Sally Yeung, Liane Martinez
Life of this patent
Estimating the term…
Abstract
Various methods and apparatus for coupling capacitors to a chip substrate are disclosed. In one aspect, a method of manufacturing is provided that includes forming a mask on a semiconductor chip substrate that has plural conductor pads. The mask has plural openings that expose selected portions of the plural conductor pads. Each of the plural openings has a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate. A conductor material is placed in the plural openings to establish plural capacitor pads.
Claims13
A method of manufacturing, comprising:
- forming a mask on a semiconductor chip substrate having a first pair of conductor pads and a second pair of conductor pads, the mask having a first plurality of openings exposing selected portions of one of the first pair of conductor pads and a second plurality of openings exposing selected portions of the other of the first pair of conductor pads, each of the first plurality of openings and the second plurality of openings having a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate, wherein the footprint provides the capability to couple different sized capacitors to the semiconductor chip substrate;
- and
- placing conductor material in the first plurality of openings and the second plurality of openings to establish plural capacitor pads.
A method of manufacturing, comprising:
- forming a mask on a semiconductor chip substrate having a first conductor pad and a second conductor pad larger than the first conductor pad;
- forming a first opening of a first footprint in the mask that exposes a portion of the first conductor pad;
- forming plural second openings of the first footprint in the mask that expose plural portions of the second conductor pad;
- and
- placing conductor material in the first opening and the plural second openings to establish a first capacitor pad on the first conductor pad and plural second capacitor pads on the second conductor pad, wherein the first footprint provides the capability to couple different sized capacitors to the semiconductor chip substrate.
A method of manufacturing, comprising:
- providing a semiconductor chip substrate having plural conductor pads and being adapted to have a semiconductor chip coupled thereto;
- forming a mask on the semiconductor chip substrate, the mask having plural openings including a first opening of a first footprint exposing a first selected portion of one of a first pair of the plural conductor pads and second opening of the first footprint exposing a second selected portion of the other of the first pair of plural conductor pads, and a first plurality of openings of the first footprint exposing selected portions of one of a second pair of the plural conductor pads and a second plurality of openings of the first footprint exposing selected portions of the other of the second pair of the plural conductor pads;
- placing conductor material in the plural openings to establish plural capacitor pads;
- determining a requisite decoupling capacitance for a combination of the semiconductor chip package and the semiconductor chip;
- and
- coupling plural capacitors to the semiconductor chip substrate, the plural capacitors collectively having the requisite decoupling capacitance, a first of the plural capacitors being coupled to the first pair of the plural conductor pads and a second of the plural capacitors being coupled to the second pair of the plural conductor pads, wherein the first footprint provides the capability to couple different sized capacitors to the semiconductor chip substrate.
Dependencies are inferred from the claim text.