Process for manufacturing a multi-drain electronic power device integrated in semiconductor substrate and corresponding device

A process, comprising:

• forming a semiconductor substrate of a first type of conductivity;
• forming on the substrate a first semiconductor layer of the first type of conductivity and of a thickness;
• forming in the first semiconductor layer implanted first sub-regions of a second type of conductivity;
• forming in the first semiconductor layer implanted second sub-regions of the first type of conductivity;
• forming on the first semiconductor layer a second semiconductor layer of the first type of conductivity and of a thickness;
• forming in the second semiconductor layer implanted third sub-regions of the second type of conductivity;
• forming in the second semiconductor layer implanted fourth sub-regions of the first type of conductivity;
• forming a surface semiconductor layer;
• forming body regions of the second type of conductivity in the surface semiconductor layer, the body regions being aligned with said first and third sub-regions;
• and
• after forming the body regions, forming, from the first and third sub-regions, electrically continuous first column regions aligned and in electric contact with said body regions, respectively, the first column regions being formed with a maximum width that is less than the thickness of the first semiconductor layer and being spaced apart from the semiconductor substrate, the first column regions having portions of elongated, substantially elliptical shape and having an alternating dopant concentration profile.