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US 8,012,829 B2Granted
Semiconductor device and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKyung Joong Joo, Han Soo Kim
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AssigneeSamsung Electronics Co., Ltd.
InventorsKyung Joong Joo, Han Soo Kim
Estimating the term…
Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region.
A method of manufacturing a semiconductor device, comprising:
A method of manufacturing a semiconductor device, comprising:
A method of manufacturing a semiconductor device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
Characterised by the shapes, relative sizes or dispositions of the floating gate electrode: having one gate at least partly in a trench
About 3 months of term left · ends 25 Jan 2027 (estimated)
1. Field
Example embodiments relate to a storage device, for example, to a device and a method for manufacturing a non-volatile and electrically erasable semiconductor memory device, for example, a flash memory.
2. Description of the Related Art
The above and other features and advantages of example embodiments will become more apparent by describing them in detailed with reference to the accompanying drawings.
FIG. 1 illustrates a plan view of NAND flash memory cells in accordance with example embodiments.
FIG. 2 illustrates a plan view of NOR flash memory cells in accordance with example embodiments.
Detailed example embodiments are disclosed herein. However, specific structural and/or functional details disclosed herein are merely representative for purposes of describing example embodiments. The claims may, however, may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein.
It will be understood that when a component is referred to as being “on,” “connected to” or “coupled to” another component, it can be directly on, connected to or coupled to the other component or intervening components may be present. In contrast, when a component is referred to as being “directly on,” “directly connected to” or “directly coupled to” another component, there are no intervening components present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.