Method of manufacturing the double-implant nor flash memory structure
AssigneeEon Silicon Solutions Inc.
InventorsYider Wu, Yung-Chung Lee, Yi-Hsiu Chen
Life of this patent
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Abstract
In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.
Claims6
A method of manufacturing a double-implant NOR flash memory structure, comprising the following steps:
- providing a semiconductor substrate;
- forming two gate structures on the semiconductor substrate;
- performing a lightly-doped ion implantation process, so that a lightly-doped drain (LDD) region is formed in the semiconductor substrate between the two gate structures, and two lightly-doped source regions are formed in the semiconductor substrate at two outer sides of the two gate structures;
- and then further performing a source region ion implantation process, so that two first source regions are formed in the semiconductor substrate at two outer sides of the two gate structures;
- wherein the first source regions each have a junction depth in the semiconductor substrate deeper than that of the LDD region;
- forming two facing spacer walls between the two gate structures, and the two facing spacer walls being located above the LDD region;
- performing a highly-doped ion implantation process, so that a highly-doped drain (HDD) region is formed between the two gate structures to overlap with the LDD region, and the HDD region having a junction depth in the semiconductor substrate deeper than that of the LDD region;
- performing a phosphorus ion implantation process, so that a P-doped drain region is formed in the semiconductor substrate between the two gate structures to overlap with the HDD region and the LDD region;
- and
- forming a barrier plug between the two gate structures.
Dependencies are inferred from the claim text.