Transistor performance improving method with metal gate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYuri Masuoka, Huan-Tsung Huang
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Abstract
The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.
Claims20
A method for making a semiconductor device having metal gate stacks comprising:
- forming a high k dielectric material layer on a semiconductor substrate;
- forming a first metal layer on the high k dielectric material layer;
- forming a silicon layer on the first metal layer;
- patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack;
- forming a second metal layer on the silicon layer;
- and
- performing a silicidation process to react the silicon layer and the second metal layer to fully change the silicon layer into a silicide electrode.
A method for making a semiconductor device having metal gate stacks comprising:
- forming a high k dielectric material layer on a semiconductor substrate;
- forming a first metal layer on the high k dielectric material layer;
- forming a silicon layer on the first metal layer;
- patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack having a gate length less than 50 nm;
- performing a silicidation process to fully change the silicon layer into a silicide electrode;
- forming a second metal layer on the silicon layer;
- performing an annealing to react the silicon layer and the second metal layer to form a silicide layer;
- and
- removing the unreacted second metal layer.
A method for manufacturing a semiconductor device comprising:
- forming a high k dielectric material layer on a semiconductor substrate;
- forming a first metal layer on the high k dielectric material layer, the first metal layer being in contact with the high k dielectric material layer;
- forming a silicon layer on the first metal layer, the silicon layer being in contact with the first metal layer;
- patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack having a gate length less than 50 nm;
- performing a silicidation process to change the silicon layer into a silicide electrode, the silicon layer being completely changed into the silicide layer electrode at the completion of the silicidation process, wherein the grated silicide layer has a varied silicide composition and phase that changes across the grated silicide layer
- forming a dielectric layer on sidewalls of the gate stack after the patterning the silicon layer, the first metal layer and the high k dielectric material layer;
- thereafter forming a light doped drain (LDD) features in the semiconductor substrate;
- thereafter forming a spacer on sidewalls of the dielectric layer;
- and
- thereafter forming a source and a drain.
Dependencies are inferred from the claim text.