Method of manufacturing layered chip package
AssigneesHeadway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
InventorsYoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
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AssigneesHeadway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
InventorsYoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
Estimating the term…
In a method of manufacturing a layered chip package, a layered substructure is fabricated and used to produce a plurality of layered chip packages. The layered substructure includes first to fourth substructures stacked, each of the substructures including an array of a plurality of preliminary layer portions. In the step of fabricating the layered substructure, initially fabricated are first to fourth pre-polishing substructures each having first and second surfaces. Next, the first and second pre-polishing substructures are bonded to each other with the first surfaces facing each other, and then the second surface of the second pre-polishing substructure is polished to form a first stack. Similarly, the third and fourth pre-polishing substructures are bonded to each other and the second surface of the third pre-polishing substructure is polished to form a second stack. Then, the first and second stacks are bonded to each other.
A method of manufacturing a plurality of layered chip packages, each of the layered chip packages comprising a main body having a top surface, a bottom surface, and four side surfaces, the main body including a plurality of layer portions stacked, the plurality of layer portions having their respective semiconductor chips, each of the semiconductor chips having a first surface with a device formed thereon and a second surface opposite to the first surface, the plurality of layer portions including at least two pairs of layer portions, each pair of layer portions being arranged so that the first surfaces of the respective semiconductor chips face each other,
Dependencies are inferred from the claim text.