Semiconductor wafer analysis system
AssigneeSamsung Electronics Co., Ltd.
InventorsChang-Huhn Lee, Seok-Woo Hong
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AssigneeSamsung Electronics Co., Ltd.
InventorsChang-Huhn Lee, Seok-Woo Hong
Estimating the term…
A semiconductor wafer analysis system is provided. In an embodiment, the semiconductor wafer analysis system includes a tester to test semiconductor wafers manufactured by at least one manufacturing facility, a wafer map generation module to generate wafer maps on the basis of the test results from the tester, and a wafer analysis module. The wafer analysis module may include a data generation module that divides each wafer map into a plurality of defect analysis regions and generates feature vectors representing the semiconductor wafers, and an operation module that statistically analyzes the feature vectors.
A semiconductor wafer analysis system comprising:
A semiconductor wafer analysis system comprising:
A semiconductor wafer analysis method, comprising:
Dependencies are inferred from the claim text.
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Inspection of images, e.g. flaw detection: industrial image inspection
Industrial image inspection: semiconductor; IC; Wafer
Image data processing or generation, in general
About 3 years 7 months of term left · ends 2 Jun 2030 (estimated)
This application claims priority from Korean Patent Application No. 10-2005-0133922 filed on Dec. 29, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
Embodiments of the present invention, disclosed herein, relate to a semiconductor wafer analysis system and a method of controlling the system, and more particularly, to a semiconductor wafer analysis system for analyzing and examining specific data of wafers.
The above and other features and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings, in which:
FIG. 1 is a block diagram of a semiconductor wafer analysis control system according to an embodiment of the invention;
FIG. 2 is a detailed block diagram of a semiconductor wafer analysis system shown in FIG. 1;
Advantages and features of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.
A semiconductor wafer analysis system according to an embodiment of the invention divides each wafer map into a plurality of defect analysis regions, generates feature vectors, and statistically analyzes the feature vectors so as to determine defective facilities.
FIG. 1 is a block diagram of a semiconductor wafer analysis control system according to an embodiment.