System and method for low-power echo and NEXT cancellers

#The present invention relates to data processing, transmission, and digital communication. More specifically, it is related to low-power implementation of echo and NEXT (near-end crosstalk) cancellers for precoder based DSP transceivers.

#Many multiple wireline communication systems, such as DSL (digital subscribe line) systems and gigabit Ethernet systems suffer from echo and crosstalks. Echo and NEXT (near-end crosstalk) cancellers are widely used to counter the effect of echo and NEXT noise. In 10 Gigabit Ethernet over copper (10GBase-T) system, full duplex baseband transmission is performaned over four pairs of UTP (unshield twisted pair). Each received signal is corrupted by echo from its own transmitter and NEXT interferences from three adjacent transmitters. To meet the desired throughput and target BER (10−12) requirements, echo and NEXT noise cancellation are expected to be about 55 dB and 40 dB, respectively.

#The typical way to perform echo and NEXT noise cancellation is using finite impulse response (FIR) filters in digital domain, where the replica of the echo and NEXT estimated by the FIR filters is subtracted from the received noisy signals. This straightforward approach, however, will have a significant complexity if the size of the FIR filters is large and thus leads to large power and silicon area. In the 10GBase-T transceivers, 16 long FIR filters need to be implemented for noise cancellation. Due to the extreme high symbol rate (such as 800 Mega Baud required for 10Gbase-T) and high noise cancellation level requirement, each FIR-filter based canceller can be of several hundred taps, and the number of total taps is around 7000. Implementing those filters at such a high speed requires a significant amount of power. Therefore reducing the power consumption of these FIR filters is important for a successful DSP transceiver design.

#The present invention is described with reference to the accompanying figures. The accompanying figures, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art to make and use the invention.

#Table 1 lists an encoding mapping from the sum of original input to the TH precoder and the corresponding compensation signal to its 8 bits 2's complement.

#Table 2 lists an encoding mapping from the original transmitted symbol without TH precoder to its 2's complement representation in 4 bits.

#Recently, TH precoding has been proposed to be used in 10GBase-T because it can eliminate error propagation and allow use of capacity-achieving channel codes, such as low-density parity-check (LDPC) codes, in a natural way. However, the use of TH precoding significantly increases the complexity of echo and NEXT cancellers in 10GBase-T.

#Consider the block diagram of the typical 10GBase-T transceiver for one pair in FIG. 1, where we need to implement one echo and three NEXT cancellers for each of four channels (or four pairs). These cancellers can be implemented based on adaptive FIR filters. In a straightforward design, the inputs of these echo and NEXT cancellers come from the output signal of the Tomlinson-Harashima precoder (TH precoder) associated with the same pair, i.e., the signal t(n) is used as the input to these cancellers, as shown in FIG. 2, where EC denotes echo canceller and NC denotes NEXT canceller. The problem associated with the design in FIG. 2 is that the wordlength of the signal, t(n), could be as long as 10 bits due to the use of TH precoding. While without TH precoding, x(n), a PAM-16 (16-level pulse amplitude modulation) signal of length only 4 bits, is used as the input signal to these cancellers. Therefore, word-length increase due to the precoding in 10GBase-T significantly increases the complexity of the multipliers in echo and NEXT cancellers. Since these cancellers are the largest blocks in the DSP transceiver, it is important to develop techniques to design echo & NEXT cancellers with low complexity and low power.

#It is known that the hardware complexity and power consumption of the filter are influenced by many factors such as the number of taps used, the coefficient range of the taps, and the operating speed. In this invention, we propose to reduce the wordlength of the input signal for echo & NEXT cancellers to achieve the low complexity and low power design.