Clock embedded differential data receiving system for ternary lines differential signaling
AssigneeTLI Inc.
InventorJae Gan Ko
Life of this patent
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Abstract
A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.
Claims17
A clock embedded differential data receiving system for receiving first, second and third transfer signals transferred via ternary lines, the clock embedded differential data receiving system, comprising:
- a monitoring portion which monitors voltage levels of the first, second and third transfer signals, and generates a clock signal, a first pre-data and a second pre-data, wherein the clock signal comprises a logic state according a comparison of the voltage levels between the first transfer signal and the second transfer signal, and wherein the first pre-data comprises a logic state according to a comparison of the voltage levels between the second transfer signal and the third transfer signal, and wherein the second pre-data comprises a logic state a comparison of the voltage levels between the third transfer signal and the first transfer signal;
- a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding the first pre-data and the second pre-data;
- and
- a timing controller which delays a transition time point of the clock signal with a delay phase and generates the sampling control signal,
- wherein the data generating portion comprises:
- a data sampling unit which generate a first leading data, a second leading data, a first legging data and a second legging data, wherein a value of the first leading data is determined by a value of the first pre-data at the leading transition of the sampling control signal, a value of the second leading data is determined by a value of the second pre-data at the leading transition of the sampling control signal, a value of the first legging data is determined by a value of the first pre-data at the legging transition of the sampling control signal, and a value of the second legging data is determined by a value of the second pre-data at the legging transition of the sampling control signal;
- and
- a decoder which decodes the first leading data, the second leading data, the first legging data and the second legging data to generate the output data group.
A clock embedded differential data receiving system for receiving first, second and third transfer signals transferred via ternary lines, the clock embedded differential data receiving system, comprising:
- a monitoring portion which monitors voltage levels of the first, second and third transfer signals, and generates a clock signal, a first pre-data and a second pre-data, wherein the clock signal comprises a logic state according a comparison of the voltage levels between the first transfer signal and the second transfer signal, and wherein the first pre-data comprises a logic state according to a comparison of the voltage levels between the second transfer signal and the third transfer signal, and wherein the second pre-data comprises a logic state a comparison of the voltage levels between the third transfer signal and the first transfer signal;
- a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding the first pre-data and the second pre-data;
- and
- a timing controller which delays a transition time point of the clock signal with a delay phase and generates the sampling control signal,
- wherein the timing controller comprises:
- a delay unit which delays the clock signal to generate a phase detect signal and the sampling signal, wherein the sampling signal comprises a second phase difference for the clock signal when the phase detect signal comprises a first phase difference for the clock signal, wherein the first phase difference is controlled by a bias signal;
- and
- a bias signal generating unit which generates the bias signal by comparing the phase of the phase detect signal with that of the clock signal.
A clock embedded differential data receiving system for receiving first, second and third transfer signals transferred via ternary lines, the clock embedded differential data receiving system, comprising:
- a monitoring portion which monitors voltage levels of the first, second and third transfer signals, and generates a clock signal, a first pre-data and a second pre-data, wherein the clock signal comprises a logic state according to a comparison of the voltage levels between the first transfer signal and the second transfer signal, the first pre-data comprises a logic state according to a comparison of the voltage levels between the second transfer signal and the third transfer signal, and the second pre-data comprises a logic state according to a comparison of the voltage levels between the third transfer signal and the first transfer signal;
- a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group and a special confirm signal with decoding the first pre-data and the second pre-data, wherein the special confirm signal is activated when the voltage levels of the first, second and third transfer signals are in a special order;
- and
- a timing controller which delays a transition time point of the clock signal with a delay phase, and generates the sampling control signal.
Dependencies are inferred from the claim text.