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US 8,009,783 B2Granted
Synchronous digital data transmission interface
AssigneeThales
InventorsYves Sontag, Laurent Jardin
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AssigneeThales
InventorsYves Sontag, Laurent Jardin
Estimating the term…
The field of the invention is that of transmission interfaces for synchronous digital input signals composed of bits transmitted in series at a frequency of transmission equal to a first integer multiple M of a first clock frequency. The interface according to the invention comprises at least one deserializer operating in over-sampling mode and supplying digital output samples of each bit in parallel. The output samples are transmitted at a second clock frequency, integer multiple N of a third frequency. The third frequency is substantially equal to the first frequency. Each sampled bit is substantially composed of N samples. The interface has an electronic device for frequency-locking the third frequency onto the first clock frequency. The device has means for counting the number of samples composing each sampled bit. The device also has incrementation-decrementation means for the third clock frequency configured in such a manner that the third clock frequency is increased when the number of samples is less than the integer multiple N and decreases when the number of samples is greater than N.
An interface for transmission of a synchronous digital input signal composed of bits transmitted in series at a frequency of transmission equal to a first integer multiple M of a first clock frequency, said interface comprising at least one deserializer operating in over-sampling mode and supplying digital output samples of each bit in parallel, the output samples being transmitted at a second clock frequency, integer multiple N of a third frequency, said third frequency being substantially equal to the first frequency, each sampled bit being substantially composed of N samples, a serial input signal giving M parallel signals, wherein said interface comprises an electronic device for frequency-locking the third frequency onto the first clock frequency, said device comprising:
Dependencies are inferred from the claim text.
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Speed or phase control by the received code signals, the signals containing no special synchronisation information: using the transitions of the…
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using special…
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: the phase or…
Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals: the correction…
About 1 year 10 months of term left · ends 7 Sep 2028 (estimated)
The present Application is based on International Application No. PCT/EP2006/069505, filed on Dec. 11, 2006, which in turn corresponds to French Application No. 0512960 filed on Dec. 20, 2005, and priority is hereby claimed under 35 USC §119 based on these applications. Each of these applications are hereby incorporated by reference in their entirety into the present application.
The field of the invention is that of transmission of synchronous binary digital input signals comprising a deserializer. These interfaces are better known by the acronym SDI for Serial Digital Interface and, more generally, the signals output from these interfaces are called SDI signals.
In a large number of applications requiring the processing of digital data at a high bit-rate, the transmission of the data between two processing units takes place via serial links, which allows the cabling to be reduced and the connection system between the various processing units to be simplified. In contrast, the processing of the data is performed in parallel by the processing units for reasons of efficiency.
The present invention is illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout and wherein:
FIG. 1 shows a first electronic assembly according to the prior art allowing the processing of serialized digital signals by a processing unit operating in parallel;
FIG. 2 shows a second electronic assembly according to the prior art also allowing the processing of serialized digital signals by a processing unit operating in parallel; and
As has been mentioned, the core principles of the invention are three-fold: Over-sampling of the serial signal; Determination of the number of samples composing each bit of the signal sampled; Feedback control of the sampling clock frequency as a function of the number of samples detected.
There are of course various electronic designs allowing these functions to be achieved. FIG. 3 is an exemplary block diagram of an interface for transmission of synchronous binary digital input signals according to the invention.
This device comprises: A deserializer 201; First and second identical storage registers 202 and 203; Indexing and comparison means 204; A third storage register 205; A fourth storage register 206; Conventional functions for processing parallel signals 207; Incrementation-decrementation means for the third clock frequency comprising a counter 208, a digital-analog converter 209, an amplifier 210 and a oscillator 211; A clock frequency multiplier 212 controlled by the clock signal produced by the oscillator 211.