Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines

A memory circuit comprising:

• a memory array including a plurality of memory cells, the memory array including a first group of memory cells;
• at least one precharge circuit;
• a first set of bitlines that contacts the first group of memory cells in the memory array;
• and
• a second set of bitlines that feeds through the first group of memory cells and does not contact the first group of memory cells.

A method comprising:

• providing a memory array that includes memory cells and at least one precharge circuit, the memory cells including at least a first group of memory cells;
• providing a plurality of partial wordline drivers in the memory array to be activated together in response to an address;
• and
• providing a first set of bitlines in the memory array that contacts the first group of memory cells and a second set of bitlines in the memory array that feeds through without contacting the first group of memory cells.