Card controller controlling semiconductor memory including memory cell having charge accumulation layer and control gate
AssigneeKabushiki Kaisha Toshiba
InventorHidetaka Tsuji
Life of this patent
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Abstract
A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.
Claims23
A controller which writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells, data in the first memory block and data in the second memory block being each respectively erased at a time, the controller comprising:
- an arithmetic processing device which writes m-bit data (where m is natural number greater than or equal to 2) to each of the memory cells in the first memory block and writes n-bit data (where n is natural number lower than m) the memory cells in the second memory block,
- wherein the arithmetic processing device
- writes data, which is received from a host apparatus, to the first memory block and
- writes management information on the data received from the host apparatus, to the second memory block.
A controller which controls operation of a plurality of semiconductor memories each including a plurality of memory blocks each including a plurality of nonvolatile memory cells, the semiconductor memories erasing data in the memory block units, the controller comprising:
- an arithmetic processing device which monitors a frequency of the write access to each of the memory blocks in each of the semiconductor memories and which changes, in accordance with a write access frequency to the memory blocks of the semiconductor memories, the semiconductor memories from a first operation mode in which data is written to the semiconductor memories at a time to a second operation mode in which data is written to each of the semiconductor memories.
Dependencies are inferred from the claim text.