Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage

A semiconductor device comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of bit lines, arranged corresponding to memory cell columns, each connected to the memory cells on a corresponding column;
• a plurality of cell power supply lines, arranged corresponding to the memory cell columns, each for supplying a first power supply voltage to the memory cells on a corresponding column;
• and
• a plurality of write assist circuits, arranged corresponding to the memory cell columns, each for selectively shutting off supply of said first power supply voltage to a corresponding cell power supply line according at least to a voltage on the bit line in a corresponding column in a data write operation, wherein
• each of the write assist circuits further includes a clamp element for clamping the voltage on the corresponding cell power supply line at a second power supply voltage that is lower than the first power supply voltage,
• the second power supply voltage is applied to the plurality of memory cells, and
• each of the write assist circuits further includes a voltage switching circuit responsive to the voltage on the corresponding bit line, for supplying an intermediate voltage between the first power supply voltage and a third power supply voltage to the corresponding cell power supply line when supply of the first power supply voltage to the corresponding cell power supply line stops.

A semiconductor memory device comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of bit lines, arranged corresponding to the memory cell columns, each connected to the memory cells on a corresponding column;
• a plurality of first cell power supply lines, arranged corresponding to the memory cell columns, respectively, each for transmitting a first power supply voltage to the memory cells on a corresponding column;
• a plurality of second cell power supply lines, arranged corresponding to the memory cell columns, respectively, each for transmitting a second power supply voltage to the memory cells on a corresponding column;
• and
• a plurality of write assist circuits, arranged corresponding to the memory cell columns, respectively, each for setting voltage levels of the first and second cell power supply lines in accordance with a write mode instruction signal and a column select signal, each write assist circuit providing the first and second power supply voltages to the first and second cell power supply lines on the corresponding column, respectively, when the write mode instruction signal indicates a write operation of the semiconductor memory device and the column select signal does not select the corresponding column, and reducing a voltage difference between said first and second cell power supply lines on the corresponding column from a difference between the first and second power supply voltages when the write mode instruction signal indicates the write operation and the column select signal selects the corresponding column.