Memory refresh system and operating method thereof

An operating method of a memory refresh system, comprising the steps of:

• detecting a voltage of a storage capacitor of a memory cell of a memory with a comparative detection circuit;
• generating a corresponding digital code by comparing the voltage with a reference voltage with the comparative detection circuit, and each of the memory cell having a corresponding digital code;
• forming a first state by combining the digital codes of the memory cells;
• detecting the voltages of the storage capacitors of the memory cells with the comparative detection circuit, and corresponding digital codes being generated and combined to form a second state;
• comparing the first state and the second state with a logic circuit to determine whether or not to change a refresh period of a refresh period detecting process for refreshing data stored in the memory cell;
• and
• selectively changing the refresh period or terminating the refresh period detecting process with a timing circuit according to a determination result of the logic circuit;
• wherein the refresh period is increased by two or more times if the first state and the second state have the same combination of digital codes, the refresh period is constant if the first state and the second state have a different combination of digital codes, and the logic circuit terminates the refresh period detecting process for refreshing data if the voltage of all memory cell are lower than the reference voltage.