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US 8,009,495 B2Granted
Memories with front end precharge
AssigneeS. Aqua Semiconductor, LLC
InventorG. R. Mohan Rao
Life of this patent
Estimating the term…
Abstract
Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where the device performs the operation including selectively precharging on the front end of the operation, in response to the received command, only a set of bit lines associated with the set of memory cells.
Claims18
A method, comprising:
- receiving, by a memory device including a plurality of memory cells and a plurality of bit lines associated with the plurality of memory cells, a first command to perform a first operation on a first subset of the plurality of memory cells;
- initiating, in response to receipt of the first command, a selective precharge operation, wherein the selective precharge operation results in a precharged state of a subset of the plurality of bit lines coupled to the first subset of the plurality of memory cells, and wherein the subset of the plurality of bit lines includes fewer bit lines than the plurality of bit lines;
- receiving, by the memory device, a second command to perform a second operation on a second subset of the plurality of memory cells, wherein the second subset of the plurality of memory cells differs from the first subset of the plurality of memory cells, and wherein the second subset of the plurality of memory cells is coupled to the subset of the plurality of bit lines;
- and
- performing, in response to said receiving a second command, the second operation on the second subset of the plurality of memory cells, wherein the second operation occurs during a time that the subset of the plurality of bit lines remains in the precharged state that results from the selective precharge operation initiated in response to receipt of the first command.
2 more elements
An apparatus, comprising:
- means for receiving
- a first command to perform a first operation on a first subset of a plurality of memory cells;
- means for receiving a second command to perform a second operation on a second subset of the plurality of memory cells, wherein the second subset of the plurality of memory cells differs from the first subset of the plurality of memory cells;
- means for performing a selective precharge operation in response to receipt of the first command, wherein the selective precharge operation results in a precharged state of a subset of a plurality of bit lines, wherein the subset of the plurality of bit lines is coupled to the first subset of the plurality of memory cells and to the second subset of the plurality of memory cells, and wherein the subset of bit lines comprises fewer bit lines than the plurality of bit lines;
- and
- means for performing, in response to the received second command, the second operation, wherein the second operation occurs during a time that the subset of the plurality of bit lines remains in the precharged state that results from the selective precharge operation initiated in response to receipt of the first command.
3 more elements
Dependencies are inferred from the claim text.