Semiconductor memory device implementing full-VDD bit line precharge scheme using bit line sense amplifier

A semiconductor memory device comprising:

• a bit line pair comprising a bit line and a complementary bit line;
• a sense amplifying unit comprising a first sense amplifier driven by a first current source and connected between the bit line and the complementary bit line, and a second sense amplifier driven by a second current source and connected between the bit line and the complementary bit line;
• a first precharge unit precharging, in response to a first precharge signal, a first node to which the first current source in the first sense amplifier is connected and a second node to which the second current source in the second sense amplifier is connected, wherein the first precharge unit includes:
• a first transistor connected between the first node and a power voltage terminal and controlled by the first precharge signal;
• and
• a second transistor connected between the second node and the power voltage terminal and controlled by the first precharge signal;
• and
• a second precharge unit equalizing, in response to a second precharge signal, the first node and the second node.

A semiconductor memory device comprising:

• a bit line pair comprising a bit line and a complementary bit line;
• a sense amplifying unit comprising a first sense amplifier driven by a first current source and connected between the bit line and the complementary bit line, and a second sense amplifier driven by a second current source and connected between the bit line and the complementary bit line;
• a first precharge unit precharging, in response to a first precharge signal, a first node to which the first current source in the first sense amplifier is connected and a second node to which the second current source in the second sense amplifier is connected, wherein the first precharge unit includes:
• a first transistor connected between the first node and a precharge voltage terminal and controlled by the first precharge signal;
• and
• a second transistor connected between the second node and the precharge voltage terminal and controlled by the first precharge signal;
• and
• a second precharge unit equalizing, in response to a second precharge signal, the first node and the second node.

A semiconductor memory device comprising:

• a bit line pair comprising a bit line and a complementary bit line;
• a precharge unit precharging the bit line and the complementary bit line a voltage that is a first voltage less than the precharge voltage, wherein the precharge unit includes comprises:
• a third transistor connected between a precharge voltage terminal and a connection node between the first transistor and the second transistor, and controlled by the precharge signal;
• a fourth transistor connected between the precharge voltage terminal and the bit line and controlled by the precharge signal;
• a fifth transistor connected between the precharge voltage terminal and the complementary bit line and controlled by the precharge signal;
• and
• a sixth transistor connected between the bit line and the complementary bit line and controlled by the precharge signal;
• and
• a sense amplifying unit comprising first and second transistors serially connected between the bit line and the complementary bit line to be cross-coupled to each other, wherein a gate of the first transistor is connected to the complementary bit line and a gate of the second transistor is connected to the bit line,
• wherein the first voltage is determined by the first or second transistor.

A method of configuring a semiconductor memory device comprising:

• providing a bit line to which a first memory cell is connected;
• providing a complementary bit line to which a second memory cell is connected;
• providing an asymmetric sense amplifier comprising first and second transistors connected to a first current source and connected between the bit line and the complementary bit line to be cross-coupled to each other and third and fourth transistors connected to a second current source and connected between the bit line and the complementary bit line to be cross-coupled to each other, wherein each of the first and fourth transistors has a current driving capability that is greater than that of each of the second and third transistors;
• and
• disposing the third transistor having the low current driving capability adjacent to the first memory cell and the second transistor having the low current driving capability adjacent to the second memory cell.