Semiconductor memory apparatus and test method thereof

A semiconductor memory apparatus comprising:

• a plurality of bit line pairs electrically connected to memory cells;
• a bit line sense amplifier configured to detect and amplify potentials of a bit line pair;
• a first data I/O lines electrically connected to the bit line pair through first switching transistors which are controlled to be turned on/off in response to control column selection signals;
• a second data I/O lines electrically connected to the first data I/O lines through second switching transistors which are controlled to be turned on/off in response to control I/O switching signals;
• and
• a test voltage applying unit configured to apply a test voltage to the second data I/O lines in response to a test mode signal.

A test method of a semiconductor memory apparatus that includes:

• a bit line pair electrically connected to a memory cell;
• first data I/O lines electrically connected to the bit line pair through first switching transistors;
• and
• second data I/O lines electrically connected to the first data I/O lines through second switching transistors,
• the test method comprising:
• performing a test to determine the occurrence of leakage current between the second data I/O lines, the test comprising applying a test voltage to the second data I/O lines when in a test mode.

A test method of a semiconductor memory apparatus that includes a bit line pair electrically connected to a memory cell and a bit line sense amplifier, the test method comprising:

• storing a first level data in the memory cell;
• deactivating the bit line sense amplifier when in a test mode;
• setting the bit line pair to a level of a test voltage by applying the test voltage to the bit line pair when in the test mode;
• and
• reading data stored in the memory cell after having set the bit line pairs to levels of the test voltage to determine whether the data corresponds to the first level data.