Memory interface circuit and memory system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorKwan-Yeob Chae
Life of this patent
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Abstract
The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock signal and a data strobe signal in response to a mode signal and delays the selected signal in response to the control signal. The slave delay unit selectively outputs a delayed clock signal that may be delayed by a first phase with respect to the clock signal or a delayed data strobe signal that may be delayed by a second phase with respect to the data strobe signal.
Claims21
A memory interface circuit comprising:
- a master delay unit configured to generate a control signal for controlling a delay time based on a clock signal;
- and
- a slave delay unit configured to select one of an inversion signal of the clock signal and a data strobe signal in response to a mode signal, delay the selected signal in response to the control signal, and selectively output a delayed clock signal delayed by a first phase with respect to the clock signal or a delayed data strobe signal delayed by a second phase with respect to the data strobe signal.
A memory interface circuit comprising:
- a master delay locked loop configured to generate a control signal for controlling a delay time of a first signal transmitted through a first delay path or a second signal transmitted through a second delay path based on a clock signal;
- a slave delay locked loop shared by the first delay path and the second delay path, the slave delay locked loop configured to delay the first signal transmitted through the first delay path or the second signal transmitted through the second delay path by a same phase in response to the control signal;
- an inverter configured to invert the first signal transmitted through the first delay path;
- and
- a selecting unit configured to activate one of the first delay path and the second delay path in response to a mode signal.
Dependencies are inferred from the claim text.