Memory with read cycle write back

A memory, comprising:

• a first pair of bit lines comprising a first bit line and a second bit line;
• a word line;
• a first memory cell coupled to the word line, the first bit line, and the second bit line;
• a sense amplifier including a first input, a second input, a first output, and a second output, the second output being a complementary output to the first output;
• a first pair of coupling transistors comprising a first transistor and a second transistor, wherein the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier;
• and
• a write back circuit including a first input coupled to the first output of the sense amplifier, a second input coupled to the second output of the sense amplifier, a first terminal coupled to the first bit line, and a second terminal coupled to the second bit line;
• wherein the sense amplifier determines a value stored in the first memory cell during a read cycle of the first memory cell, wherein the write back circuit writes back the determined value in the first memory cell during a write back phase of the read cycle.

A memory, comprising:

• a first pair of bit lines comprising a first bit line and a second bit line;
• a word line;
• a first memory cell coupled to the word line, the first bit line, and the second bit line;
• a sense amplifier including a first input, a second input, a first output, and a second output, the second output being a complementary output to the first output;
• a first pair of coupling transistors comprising a first transistor and a second transistor, wherein the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier;
• and
• a write back circuit including a first input coupled to the first output of the sense amplifier, a second input coupled to the second output of the sense amplifier, a first terminal coupled to the first bit line, and a second terminal coupled to the second bit line;
• wherein:
• the first transistor includes a control electrode for receiving a control signal and the second transistor includes a control electrode for receiving the control signal;
• the control signal causes the first transistor and the second transistor to become conductive during a first portion of a read cycle of the first memory cell and non-conductive during a second portion of the read cycle.

A memory, comprising:

• a first pair of bit lines comprising a first bit line and a second bit line;
• a word line;
• a first memory cell coupled to the word line, the first bit line, and the second bit line;
• a sense amplifier including a first input, a second input, a first output, and a second output, the second output being a complementary output to the first output;
• a first pair of coupling transistors comprising a first transistor and a second transistor, wherein the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier;
• and
• a write back circuit including a first input coupled to the first output of the sense amplifier, a second input coupled to the second output of the sense amplifier, a first terminal coupled to the first bit line, and a second terminal coupled to the second bit line;
• wherein the write back circuit comprises:
• a third input for receiving a data signal;
• a fourth input for receiving a complementary signal of the data signal;
• a first multiplexer including a first input coupled to the third input, a second input coupled to the first output of the sense amplifier, and an output, wherein the output of the first multiplexer provides a first control signal;
• a second multiplexer including a first input coupled to the fourth input, a second input coupled to the second output of the sense amplifier, and an output, wherein the output of the second multiplexer provides a second control signal;
• wherein during a read cycle of the first memory cell, the first multiplexer couples its second input to its output and the second multiplexer couples its second input to its output;
• wherein during a write cycle of the first memory cell, the first multiplexer couples its first input to its output and the second multiplexer couples its first input to its output;
• wherein the first control signal and the second control signal are used for determining whether to provide a current path from the first bit line to a voltage supply terminal or to provide a current path from the second bit line to a voltage supply terminal to write a first value or a second value, respectively, to the first memory cell during a write cycle or a write back phase of a read cycle of the first memory cell.

A memory, comprising:

• a first pair of bit lines comprising a first bit line and a second bit line;
• a word line;
• a first memory cell coupled to the word line, the first bit line, and the second bit line;
• a sense amplifier including a first input, a second input, a first output, and a second output, the second output being a complementary output to the first output;
• a first pair of coupling transistors comprising a first transistor and a second transistor, wherein the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier;
• and
• a write back circuit including a first input coupled to the first output of the sense amplifier, a second input coupled to the second output of the sense amplifier, a first terminal coupled to the first bit line, and a second terminal coupled to the second bit line;
• wherein:
• the first memory cell is an SRAM memory cell;
• the first memory cell includes:
• a first storage node;
• a second storage node;
• a first access transistor including a control terminal connected to the word line, a first current terminal connected to the first bit line, and a second current terminal connected to the first storage node;
• a second access transistor including a control terminal connected to the word line, a first current terminal connected to the second bit line, and a second current terminal connected to the second storage node.

A memory, comprising:

• a first pair of bit lines comprising a first bit line and a second bit line;
• a word line;
• a first memory cell coupled to the word line, the first bit line, and the second bit line;
• a sense amplifier including a first input, a second input, a first output, and a second output, the second output being a complementary output to the first output;
• a first pair of coupling transistors comprising a first transistor and a second transistor, wherein the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier;
• and
• a write back circuit including a first input coupled to the first output of the sense amplifier, a second input coupled to the second output of the sense amplifier, a first terminal coupled to the first bit line, and a second terminal coupled to the second bit line;
• a second pair of bit lines comprising a third bit line and a fourth bit line;
• a second memory cell coupled to the word line and to the second pair of bit lines;
• a second pair of coupling transistors comprising a third transistor and a fourth transistor, wherein the third transistor is coupled between the third bit line and the first input of the sense amplifier and the fourth transistor is coupled between the fourth bit line and the second input of the sense amplifier;
• and
• a second write back circuit including a first input coupled to the first output of the sense amplifier, a second input coupled to the second output of the sense amplifier, a first terminal coupled to the third bit line, and a second terminal coupled to the fourth bit line.

A method for performing a read cycle of a memory cell of a memory, the memory includes a first pair of bit lines including a first bit line and a second bit line, a word line, a first memory cell, and a sense amplifier, the first memory cell coupled to the word line, the first bit line, and the second bit line, the method for performing a read cycle of the first memory cell comprising:

• enabling the word line;
• using the sense amplifier to determine a stored value of the memory cell during the step of enabling the word line;
• decoupling the sense amplifier from the first pair of bit lines during the step of enabling;
• and
• writing back the stored value as determined by the sense amplifier to the memory cell during the step of enabling and during a time after the step of decoupling.

A method for performing a read cycle of a first memory cell of a memory, the memory includes a first pair of bit lines including a first bit line and a second bit line, a word line, a first memory cell coupled to the word line and to the first pair of bit lines, and a sense amplifier, the method for performing a read cycle of the first memory cell comprising:

• enabling the word line to couple a first storage node and a second storage node of the first memory cell to the first bit line and the second bit line, respectively, to generate a voltage differential between the first bit line and the second bit line, wherein the step of enabling the word line includes an initial portion and a subsequent portion;
• coupling the first pair of bit lines to the sense amplifier during the initial portion of the step of enabling;
• determining a value stored in the first memory cell by the sense amplifier;
• decoupling the sense amplifier from the first pair of bit lines at an end of the initial portion;
• and
• writing back to the first memory cell the determined value during the subsequent portion of the step of enabling the word line, the writing back including biasing one of the first bit line or the second bit line to a supply voltage based on the determined value.