Semiconductor memory device

A semiconductor memory device, comprising:

• a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array block including memory cells each having a transistor with a floating body and being configured to write/read data by performing a bipolar junction transistor operation for selected memory cells;
• a reference voltage generator including a reference memory cell and a plurality of resistors, the reference voltage generator configured to generate a reference voltage for bit line sensing corresponding to a current flowing to the reference memory cell during a data read operation, the reference memory cell configured to receive a source line voltage at a first terminal, receive a word line signal through a gate terminal, induce a current at a second terminal and write and read data;
• a plurality of resistors connected in series between the reference memory cell and a ground, the plurality of resistors being configured to receive the current from the reference memory cell, distribute a voltage, and generate the target reference voltage;
• first and second prechargers configured to precharge a bit line connected to non-selected memory cells to the reference voltage in response to first and second precharge control signals during the data read operation;
• and
• a sense amplifier configured to sense and amplify a voltage difference between a bit line connected to the selected memory cells and a bit line connected to the non-selected memory cells during the data read operation.

A semiconductor memory device, comprising:

• a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array block including memory cells each having a transistor with a floating body and being configured to write/read data by performing a bipolar junction transistor operation for selected memory cells;
• a reference voltage generator including a reference memory cell, the reference voltage generator configured to generate a reference voltage for bit line sensing corresponding to a current flowing to the reference memory cell during a data read operation;
• first and second prechargers configured to precharge a bit line connected to non-selected memory cells to the reference voltage in response to first and second precharge control signals during the data read operation;
• and
• a sense amplifier configured to sense and amplify a voltage difference between a bit line connected to the selected memory cells and a bit line connected to the non-selected memory cells during the data read operation, wherein the reference voltage generator includes:
• a target reference voltage generator including the reference memory cell, the reference memory cell being configured to receive a source line voltage and generate a target reference voltage in response to a word line signal and induce a current at a terminal thereof, and
• a plurality of resistors connected in series between the reference memory cell and a ground, the plurality of resistors being configured to receive the current induced from the reference memory cell, distribute a voltage, and generate the target reference voltage,
• a comparator configured to receive the target reference voltage and a presently operating bit line precharge voltage, compare the two voltages, and output a variable bit line precharge voltage as the reference voltage.