System and method for mitigating reverse bias leakage
AssigneeMicron Technology, Inc.
InventorJohn D. Porter
Life of this patent
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Abstract
The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines.
Claims26
A memory device comprising:
- an array of memory cells;
- a gap located adjacent to the array;
- and
- clamp circuitry located in the gap, wherein the clamp circuitry is configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation.
A memory device comprising:
- one or more arrays of memory cells, wherein the memory cells are coupled to one or more data lines;
- one or more row decoders connected to a first side of the one or more arrays;
- one or more column decoders connected to a second side of the one or more arrays, wherein the second side is adjacent to the first side;
- one or more gaps located adjacent to the one or more row decoders and the one or more column decoders;
- and
- clamp circuitry located in the one or more gaps, wherein:
- the clamp circuitry includes one or more selectable paths;
- each of the selectable paths is configured to pull the one or more data lines to a different voltage;
- a first selectable path is configured to pull the one or more data lines to approximately one p-channel metal oxide semiconductor (PMOS) transistor threshold voltage (Vt) above a reference voltage;
- a second selectable path is configured to pull the one or more data lines to approximately one PMOS transistor Vt above ground;
- a third selectable path is configured to pull the one or more data lines to approximately one thick oxide n-channel metal oxide semiconductor (NMOS) transistor Vt above ground;
- and
- a fourth selectable path is configured to pull the one or more data lines to approximately one thin oxide NMOS Vt above ground.
A memory device comprising:
- an array of memory cells divided into two or more subarrays;
- a column decoder connected to the array;
- one or more spaces that separate the column decoder into a number of portions, wherein each portion is associated with a different subarray;
- and
- circuitry located in the one or more spaces, wherein the circuitry is configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation.
A method for operating one or more arrays of memory cells, comprising:
- selectively coupling one or more data lines to which one or more unselected memory cells are coupled to clamp circuitry located in a gap that is adjacent to the one or more arrays;
- and
- pulling the one or more data lines to a selected voltage using the clamp circuitry.
A memory device comprising:
- an array of memory cells;
- a gap located adjacent to the array;
- and
- clamp circuitry located in the gap, wherein the clamp circuitry is configured to reduce a reverse bias voltage associated with one or more unselected memory cells during a programming operation as compared to a reverse bias voltage associated with the one or more unselected memory cells when the one or more unselected memory cells are held near ground.
A memory device comprising:
- an array of memory cells;
- a gap located adjacent to the array;
- and
- clamp circuitry located in the gap, wherein the clamp circuitry includes one or more transistors selected from the group consisting of:
- a p-channel metal oxide semiconductor (PMOS) transistor having a gate coupled to ground;
- a PMOS transistor having a gate coupled to one or more reference voltages;
- a thick oxide diode connected n-channel metal oxide semiconductor (NMOS) transistor;
- and
- a thin oxide diode connected NMOS transistor.
Dependencies are inferred from the claim text.