Semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorJi-Hyae Bae
Life of this patent
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Abstract
A semiconductor memory device includes training drivers configured to transmit one of data and a predetermined training data pattern from a first data lines to a second data lines in response to a training control signal which is produced by decoding a read training command; and the second data lines configured to transmit an output of the training drivers. The semiconductor memory device according to the present invention can exactly measure a delay time, which is changed according to the surrounding environments between a semiconductor memory device and a data processing unit, through a data training and operation timing can be also adjusted based on the measured delay time.
Claims17
A semiconductor memory device comprising:
- a training driver configured to transmit one of data input from a first data line and a predetermined training data pattern to a second data line in response to a training control signal which is produced by decoding a read training command;
- and
- the second data line configured to transmit an output of the training driver,
- wherein the training driver transmits the predetermined training data pattern to the second data line during an activation period of the training control signal and transmits the data input from the first data line to the second data line during an inactivation period of the training control signal,
- wherein the training data pattern is logically fixed in the training driver and is generated in the training driver.
A semiconductor memory device comprising:
- a plurality of training drivers for transmitting a predetermined training data pattern to an plurality of I/O pads in response to an activation of a training control signal which is produced by decoding a read training command;
- and
- a plurality of first data lines for transmitting a data from a plurality of unit cells to the plurality of training drivers during a read operation and a write operation,
- wherein the plurality training drivers transmit the predetermined training data pattern to the second data line during an activation period of the training control signal and transmits the data to the second data line during an inactivation period of the training control signal,
- wherein the training data pattern is logically fixed in the plurality of training drivers and is generated in the plurality of training drivers.
A semiconductor memory device comprising:
- training drivers for receiving data from first data lines and transmitting a predetermined data training pattern to second data lines during an activation period of a training control signal and the data received from the first data lines to the second data lines during an inactivation period of the training control signal, which is produced by decoding a read training command;
- and
- the second data lines for transmitting an output of the training drivers,
- wherein the training driver transmits the predetermined training data pattern to the second data line during an activation period of the training control signal and transmits the data received from the first data lines to the second data line during an inactivation period of the training control signal,
- wherein the training data pattern is logically fixed in the training drivers and is generated in the training drivers.
Dependencies are inferred from the claim text.