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US 8,009,481 B2Granted
System and method for bit-line control
AssigneeInfineon Technologies AG
InventorThomas Nirschl
Life of this patent
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Abstract
In one embodiment, a bit-line driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The bit-line driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor.
Claims21
A bit-line driver comprising:
- a first driver comprising
- a source terminal coupled to a high-voltage supply bus, and
- a drain terminal coupled to the bit-line;
- a second driver comprising
- a source terminal coupled to a high-voltage return bus, and
- a drain terminal coupled to the bit line;
- a first pre-driver directly connected to a gate terminal of the first driver;
- and
- a second pre-driver directly connected to a gate terminal of the second driver, wherein the first and second drivers comprise a first type of transistor, and the first and second pre-drivers comprise a second type of transistor, wherein the first type of transistor is rated at a higher voltage than the second type of transistor, and wherein the first and second pre-drivers each comprises a storage element.
6 more elements
A memory comprising:
- a memory array comprising a plurality of storage cells;
- a bit-line coupled to at least one storage cell;
- and
- a bit-line driver comprising
- a first driving transistor coupled to the bit-line,
- a first low-voltage pre-driver directly connected to a control terminal of the first driving transistor, the first low-voltage pre-driver comprising at least one low-voltage transistor, the at least one low-voltage transistor rated to operate at lower voltages than the driving transistor,
- a second driving transistor coupled to the bit line,
- a second low-voltage pre-driver coupled to a control terminal of the second driving transistor, the second low-voltage pre-driver comprising at least one low-voltage transistor, wherein the first and second pre-drivers comprise latches.
5 more elements
A semiconductor circuit comprising:
- a first level shifter coupled to a first input;
- a first pre-driver comprising
- an input node coupled to an output of the first level shifter, and
- a supply node coupled to a first supply bus;
- a PMOS transistor comprising
- a gate coupled to an output of the first pre-driver,
- a drain coupled to a bit-line,
- and a source coupled to a second supply bus;
- a second level shifter coupled to a second input;
- a second pre-driver comprising
- an input node coupled to an output of the second level shifter, and
- a supply node coupled to a third supply bus;
- and
- an NMOS transistor comprising
- a gate coupled to an output of the second pre-driver,
- a drain coupled to a bit-line, and
- a source coupled to a fourth supply bus, wherein the PMOS and NMOS transistors are rated at a higher voltage than the first and second pre-drivers.
14 more elements
A bit-line driver comprising:
- a first driver comprising
- a source terminal coupled to a high-voltage supply bus, and
- a drain terminal coupled to the bit-line;
- a second driver comprising
- a source terminal coupled to a high-voltage return bus, and
- a drain terminal coupled to the bit line;
- a first pre-driver coupled to a gate terminal of the first driver;
- and
- a second pre-driver coupled to a gate terminal of the second driver, wherein the first and second drivers comprise a first type of transistor, and the first and second pre-drivers comprise a second type of transistor, wherein the first type of transistor is rated at a higher voltage than the second type of transistor, wherein
- the first pre-driver comprises a supply node coupled to a first low-voltage supply bus and a ground node coupled to a first low-voltage return bus, and
- the second pre-driver comprises a supply node coupled to a second low-voltage supply bus and a ground node coupled to a second low-voltage return bus.
8 more elements
A memory comprising:
- a memory array comprising a plurality of storage cells;
- a bit-line coupled to at least one storage cell;
- and
- a bit-line driver comprising
- a first driving transistor coupled to the bit-line,
- a first low-voltage pre-driver coupled to a control terminal of the first driving transistor, the first low-voltage pre-driver comprising at least one low-voltage transistor, wherein,
- the first low-voltage pre-driver is configured to drive a shut-down voltage, the shut-down voltage comprising a first set voltage below a turn-on threshold of the first driving transistor in response to a first input voltage, and
- the first low-voltage pre-driver is further configured to drive a turn-on voltage, the turn-on voltage comprising a second set voltage above the turn-on threshold of the first driving transistor in response to a second input voltage.
5 more elements
Dependencies are inferred from the claim text.