Back to results
US 8,009,478 B2Granted
Non-volatile memory apparatus and methods
AssigneeMicron Technology, Inc.
InventorPaul D. Ruby
Life of this patent
Estimating the term…
Abstract
Some embodiments include apparatus and methods having memory cells coupled in series and a module to cause an application of voltages with at least three different values to gates of the memory cells during an operation to retrieve information stored in at least one of the memory cells. Additional apparatus and methods are described.
Claims17
An apparatus comprising:
- memory cells coupled in a series, each of the memory cells including a gate, the gates being electrically isolated from each other;
- and
- a module to cause an application of voltages with at least three different values to gates of the memory cells during an operation to retrieve information stored in a selected memory cell of the memory cells, wherein the memory cells include a first memory cell immediately adjacent a first side of the selected memory cell and a second memory cell immediately adjacent a second side of the selected memory cell, wherein the module is to apply the voltages such that a voltage applied to the gate of each of the first and second memory cells is greater than a voltage applied to the gates of other memory cells in the series, and, wherein the module includes a circuit to apply a first voltage included in the voltages to a gate of a first memory cell of the memory cells and to apply a second voltage included in the voltages to a gate of a second memory cell of the memory cells, such that the first voltage has a value approximately ten percent greater than a value of the second voltage.
An apparatus comprising:
- a first memory cell including a first gate, a second memory cell including a second gate, a third memory cell including a third gate, and a fourth memory cell including a fourth gate, the first, second, third, and fourth memory cells coupled in series, the second memory located between the first and third memory cells, the third memory located between the second and fourth memory cells;
- and
- a module to cause a selective application a first voltage having a first value to the first gate during an operation to retrieve information stored in the first memory cell, a second voltage having a second value greater than the first value to the second gate during the memory operation, a third voltage having a third value less than the second value to the third gate during the memory operation, and a fourth voltage having a fourth value different from the third value to the fourth gate during the memory operation.
An apparatus comprising:
- a first memory cell including a gate to receive a first voltage having a first value during a during an operation to retrieve information stored in the first memory cell;
- second memory cells coupled in series with the first memory cell and located on a first side of the first memory cell, each of the second memory cells including a second gate, wherein at least two of the second gates receive second voltages having different values during the operation;
- and
- third memory cells coupled in series with the first memory cell and located on a second side opposite from the first side of the first memory cell, each of the third memory cells including a third gate, wherein at least two of the third gates receive third voltages have different values during the operation.
1 more element
A method comprising:
- receiving a command to read information stored in at least one of memory cells of a device during an operation of the device, the memory cells coupled in series, each of the memory cells including a gate, the gates of the memory cells being electrically isolated from each other;
- applying voltages having at least three different values to different gates during the operation;
- during the operation, sensing signals on lines coupled to a selected memory cell among the memory cells to determine information stored in the selected memory cell;
- applying a first voltage of the voltages to a first gate of a first memory cell of the memory cells;
- and
- applying a second voltage of the voltages to a second gate of a second memory cell of the memory cells, wherein the first voltage has a value approximately ten percent greater than a value of the second voltage.
3 more elements
A method comprising:
- applying a first voltage having a first value to a first gate of a first memory cell of a device during a read operation of the device;
- applying a second voltage having a second value to a second gate of a second memory cell of the device during the read operation;
- and
- applying a third voltage having a third value to a third gate of a third memory cell of the device during the read operation, the first, second, and third memory cells coupled in series, wherein the third value is greater than the second value and the second value is greater than the first value, wherein the first value is zero volts and the third value is approximately 600 millivolts greater than the second value.
1 more element
A method comprising:
- applying a first voltage having a first value to a first gate of a first memory cell of a device during a read operation of the device;
- applying second voltages to gates of second memory cells coupled in series with the first memory cell and located on a first side of the first memory cell, wherein at least two of the second voltages have different values;
- and
- applying third voltages to gates of third memory cells coupled in series with the first memory cell and located on a second side opposite from the first side of the first memory cell, wherein at least two of the third voltages have different values.
1 more element
Dependencies are inferred from the claim text.