Integrated circuit and method of forming an integrated circuit

An integrated circuit comprising:

• a carrier having a surface;
• an insulating layer over the carrier;
• a memory cell array;
• and
• a conductive line comprising a lower line portion and an upper line portion, to which a plurality of memory cell transistors are connected, the lower line portion and the upper line portion directly contacting the insulating layer, wherein a slope along a side wall profile of the conductive line in a direction perpendicular to the surface includes a discontinuity between the lower line portion and the upper line portion,
• wherein a bottom side of the conductive line is in contact with a surface of the carrier,
• wherein the upper line portion is partly formed directly above a gate portion of the memory cell transistors, and
• wherein the insulating layer directly contacts the surface of the carrier between the lower line portion and the gate portion of the memory cell transistors.

A non-volatile semiconductor memory device comprising:

• a carrier having a surface;
• an insulating layer over the carrier;
• a memory cell array comprising NAND strings, wherein each NAND string comprises multiple non-volatile memory transistors connected in series;
• a source line, to which one end of the NAND strings is connected via select transistors, the source line further comprising a lower source line portion and an upper source line portion, the lower source line portion and the upper source line portion directly contacting the insulating layer, wherein the lower source line portion includes a side wall profile that is different from the side wall profile of the upper source line portion, and
• wherein a bottom side of the lower source line portion is in contact with the surface of the carrier,
• wherein the upper source line portion is partly formed directly above a gate portion of the select transistors, and
• wherein the insulating layer directly contacts the surface of the carrier between the lower source line portion and the gate portion of the select transistors.

A memory device comprising:

• a carrier having a surface;
• an insulating layer over the carrier;
• storage means for storing an electric charge;
• and
• a conductive line connected to a plurality of the storage means, further comprising a lower line portion and an upper line portion, the lower line portion and the upper line portion directly contacting the insulating layer, wherein the lower line portion includes a side wall profile that is different from the side wall profile of the upper line portion,
• wherein a bottom side of the lower line portion is in contact with the surface of the carrier,
• wherein the upper line portion is partly formed directly above a gate portion of the storage means, and
• wherein the insulating layer directly contacts the surface of the carrier between the lower line portion and the gate portion of the storage means.

A non-volatile semiconductor memory device comprising:

• a carrier having a surface;
• an insulating layer over the carrier;
• a memory cell array comprising NAND strings, wherein each NAND string comprises multiple non-volatile memory transistors connected in series;
• and
• a source line comprising a lower source line portion and an upper source line portion, to which one end of the NAND strings is connected via select transistors, the lower source line portion and the upper source line portion directly contacting the insulating layer, wherein a slope of a side wall profile of the source line in a direction perpendicular to the surface includes a discontinuity between the lower source line portion and the upper source line portion,
• wherein a bottom side of the source line is in contact with the surface of the carrier,
• wherein the upper source line portion is partly formed directly above a gate portion of the select transistors, and
• wherein the insulating layer directly contacts the surface of the carrier between the lower source line portion and the gate portion of the select transistors.

A method of forming a conductive line comprising:

• forming an insulating layer over a surface of a carrier;
• isotropically etching the insulating layer to provide an upper trench portion;
• anisotropically etching the insulating layer to provide a lower trench portion, thereby uncovering a plurality of active areas at the surface of the carrier and a plurality of source regions of select transistors of a NAND flash memory device;
• and
• filling the lower and the upper trench portions with a conductive material to provide the conductive line comprising an upper line portion and a lower line portion,
• wherein the upper line portion is partly formed directly above a gate portion of the select transistors, and
• wherein the insulating layer directly contacts the surface of the carrier between the lower line portion and the gate portion of the select transistors.

A method of forming a conductive line comprising:

• forming an insulating layer over a surface of a carrier;
• anisotropically etching the insulating layer to provide a trench therein;
• isotropically etching an etch mask structure provided on the insulating layer to enlarge openings of the etch mask structure;
• anisotropically etching the insulating layer, thereby recessing the trench to expose a plurality of active areas in a lower trench portion and broadening the trench in an upper trench portion;
• and
• filling the lower and the upper trench portions with a conductive material to provide the conductive line comprising an upper line portion and a lower line portion.

A method of forming a conductive line comprising:

• forming an insulating layer over a surface of a carrier;
• etching a lower trench portion and an upper trench portion in such a manner that a ratio of widths of the upper trench portion and the lower trench portion is independent from the thickness of the insulating layer, and uncovering, by etching the lower trench portion, a plurality of source regions of select transistors of a NAND flash memory device;
• and
• filling the lower and the upper trench portions with a conductive material,
• wherein the upper trench portion is partly formed directly above a gate portion of the select transistors, and
• wherein the insulating layer directly contacts the surface of the carrier between the lower trench portion and the gate portion of the select transistors.