Semiconductor memory device using variable resistor
AssigneeSamsung Electronics Co., Ltd.
InventorByung-Gil Choi
Life of this patent
Estimating the term…
Abstract
Example embodiments relate to a variable resistance semiconductor memory device including: a plurality of memory blocks belonging to different memory sectors and alternately arranged in a memory bank including the memory sectors so as to be adjacent to each other; and a line selecting unit simultaneously selecting word lines of the plurality of memory blocks and simultaneously selecting bit lines of the memory blocks belonging to the same memory sector among the plurality of memory blocks in an access operation mode.
Claims10
A variable resistance semiconductor memory device comprising:
- a plurality of memory blocks belonging to different memory sectors and alternately arranged in a memory bank including the memory sectors so as to be adjacent to each other;
- and
- a line selecting unit simultaneously selecting word lines of the plurality of memory blocks and simultaneously selecting bit lines of the memory blocks belonging to the same memory sector among the plurality of memory blocks in an access operation mode.
A variable resistance semiconductor memory device comprising:
- first group memory blocks belonging to a first memory sector of a memory bank and arranged with a gap therebetween;
- second group memory blocks belonging to a second memory sector of the memory bank and arranged between the first group memory blocks;
- and
- a line selecting unit simultaneously activating word lines of the first and second group memory blocks and simultaneously activating bit lines of the first group memory blocks or the second group memory blocks in an access operation mode.
A variable resistance semiconductor memory device comprising:
- first group memory blocks belonging to a first memory sector of a memory bank and including sub memory blocks that are arranged with a gap therebetween;
- second group memory blocks belonging to a second memory sector of the memory bank and arranged between the sub memory blocks of the first group memory blocks;
- and
- a line selecting unit simultaneously activating word lines of the first and second group memory blocks and simultaneously activating bit lines of the first group memory blocks or the second group memory blocks in an access operation mode.
Dependencies are inferred from the claim text.