Nonvolatile semiconductor memory

A nonvolatile semiconductor memory comprising:

• first and second select gate transistors;
• memory cells connected in series between the first and second select gate transistors;
• a source line connected to the first select gate transistor;
• a bit line connected to the second select gate transistor;
• a selected word line which is connected to a selected memory cell as a target of a verify reading among the memory cells;
• a non-selected word line which is connected to a non-selected memory cell except the selected memory cell among the memory cells;
• a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line;
• and
• a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.