Multiple level cell memory device with single bit per cell, re-mappable memory block
AssigneeRound Rock Research, LLC
InventorFrankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode.
Claims17
A memory system having a memory array with a plurality of memory cell groupings, the plurality of memory cell groupings comprising:
- a subset of the plurality of the memory cell groupings wherein each grouping of the subset is configured to operate in one of at least a first density and a second density;
- a configuration register configured to assign the groupings of memory to one of the at least first density and second density;
- at least one error free memory cell grouping that is configured to operate only in a first density, wherein the first density is lower than the second density;
- and
- control circuitry for controlling remapping of a second error free memory cell grouping to the at least one error free memory cell grouping such that further accesses to the second error free memory cell grouping are performed by the at least one error free memory cell grouping.
A memory device comprising:
- a memory array comprising a plurality of memory cells organized into memory blocks including a first memory block that operates only in a lower density mode;
- and
- control circuitry that controls which memory blocks store data in a high density mode and which memory blocks store data in the lower density mode, the control circuitry further configured to control remapping of a second memory block to the first memory block such that further accesses to the second memory block are performed by the first memory block.
A method for configuring density/performance of a plurality of memory blocks in a memory device having a configuration register, the method comprising:
- loading the configuration register with memory density configuration data, wherein the loading of the configuration register is performed when the memory device is initialized and/or powered up;
- receiving a memory command;
- determining if the memory command is a read or write command;
- reading the configuration data prior to read or write operation in response to command;
- performing either a high density memory operation or a lower density memory operation in response to the configuration data and the command;
- and
- when a first memory block accessed by a low density memory operation includes a defective cell, remapping a second memory block to the first memory block such that further accesses to the second memory block are performed by the first memory block.
Dependencies are inferred from the claim text.