Cell structure for dual port SRAM

A multi-port static random access memory (SRAM) cell comprising:

• first and second cross-coupled inverters having a data storage node and a data bar storage node, each inverter comprising a pull-up transistor and a pull down device, wherein each pull down device comprises at least a pair of pull down transistors having commonly connected source, drain and gate terminals;
• first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the data storage node and a second pass gate transistor coupled to the data bar storage node, each pass gate transistor being coupled to a respective bit line conductor;
• a first power supply conductor Vdd and a pair of second power supply conductors Vss;
• a first metallization layer including conductors for making local intra-cell connections between the pass gate transistors and the pull down devices;
• a second metallization layer formed over the first metallization layer containing the bit line conductors and power supply conductors;
• and
• a third metallization layer formed over the second metallization layer containing the word line conductors.

A multi-port static random access memory (SRAM) cell comprising:

• first and second cross-coupled inverters having a data storage node and a data bar storage node, each inverter comprising a pull-up transistor and a pull down device;
• first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the data storage node and a second pass gate transistor coupled to the data bar storage node, each pass gate transistor being coupled to a respective bit line conductors;
• and
• a first power supply conductor Vdd and a pair of second power supply conductors Vss,
• wherein the bit line conductors and power supply conductors are formed in a common metallization layer, and
• wherein the bit line and power supply conductors are disposed in parallel, with the first power supply conductor Vdd centered among the conductors and the pair of second power supply conductors Vss disposed adjacent the first power supply conductor on opposite sides of the first power supply conductor.