SRAM device, and SRAM device design structure, with adaptable access transistors

A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising a SRAM device design including a pair of MCSFETs connected as access transistors, each of the access transistors is electrically connected to a wordline control circuit including a single wordline conductor connected to a gate of each said MCSFET of said pair for controlling said MCSFET access transistor, said wordline control circuit including a switch device for driving a respective gate of each said MCSFET via said single wordline conductor at a voltage between a first threshold voltage Vt1 and a second threshold voltage Vt2 for a read operation of said SRAM, and, said switch device for driving a respective gate of each said MCSFET via said single wordline conductor at a voltage greater than Vt2 for a write operation.