Device and method for using dynamic cell plate sensing in a DRAM memory cell

A memory device, comprising:

• a memory array including a plurality of memory cells, wherein each of the plurality of memory cells includes a first capacitor coupled to an electrically isolated cell plate conductor, a second capacitor coupled to the electrically isolated cell plate conductor, and first and second pass transistors electrically coupled in series to opposing ends of the first capacitor and the second capacitor and coupled between a first digit line and a second digit line, the first and second pass transistors further coupled for control by a first wordline being substantially parallel and non-overlapping to the electrically isolated cell plate conductor;
• and
• a plurality of sense amplifiers configured for selectably coupling with pairs of the first and second digit lines.

A semiconductor wafer including an integrated circuit configured as a memory array, the memory array including a plurality of memory cells, wherein each of the plurality of memory cells includes a first capacitor coupled to an electrically isolated cell plate conductor, a second capacitor coupled to the electrically isolated cell plate conductor, and first and second pass transistors electrically coupled in series to opposing ends of the first capacitor and the second capacitor, and coupled between a first digit line and a second digit line, the first and second pass transistors further coupled for control by a first wordline being substantially parallel and non-overlapping to the electrically isolated cell plate conductor.

An electronic system including an input device, an output device, a memory device, and a processor device coupled to the input, output and memory devices, the memory device comprising a memory array including a plurality of memory cells, wherein each of the plurality of memory cells includes a first capacitor coupled to an electrically isolated cell plate conductor, a second capacitor coupled to the electrically isolated cell plate conductor, and first and second pass transistors electrically coupled in series to opposing ends of the first capacitor and the second capacitor coupled between a first digit line and a second digit line, the first and second pass transistors further coupled for control by a first wordline being substantially parallel and non-overlapping to the electrically isolated cell plate conductor.

A memory device, comprising:

• a memory array including a plurality of memory cells, wherein each of the plurality of memory cells includes a first pass transistor and a second pass transistor and a commonly coupled capacitor therebetween having a conductive interconnection plate that is electrically isolated from other commonly coupled capacitors of the plurality of memory cells, wherein the conductive interconnection plate of each of the plurality of memory cells is non-overlapping to a wordline coupled with the first pass transistor and the second pass transistor;
• and
• a plurality of sense amplifiers configured for selectably coupling with a complementary pair of digit lines.