Write current compensation using word line boosting circuitry

A memory array, comprising:

• a plurality of resistive random access memory (RRAM) cells arranged into rows and columns, each cell comprising a switching device connected to an RRAM element comprising an upper electrode, a lower electrode and an intervening oxide layer;
• and
• a write circuit adapted to sequentially write data to the memory cells along a selected row or a selected column by applying a first gate control voltage to the switching devices of said memory cells written in an easy direction and by applying a higher, second gate control voltage to the switching devices of said memory cells written in an opposing hard direction.

A portable storage device, comprising:

• a non-volatile memory cell adapted to alternately store first and second logical data values, the memory cell comprising a resistive random access memory (RRAM) element coupled to a switching device comprising respective drain, source and gate terminals;
• and
• a write circuit adapted to write the first logical data value to the RRAM element by applying a first gate control voltage to the gate terminal while passing a first write current in an easy programming direction through the cell, and to write the second logical data value to the RRAM element by applying a boosted, second gate control voltage to the gate terminal while passing an opposing second write current in a hard programming direction through the cell.