Method and circuit for eFuse protection

#1. Field

#This disclosure relates generally to electronically programmable fuses (eFuse), and more specifically, to a method and circuit for protecting eFuses from accidental programming during power-up and electrostatic discharge (ESD) events.

#2. Related Art

#The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

#FIG. 1 is an illustrative characterization plot of current versus voltage for an eFuse stressed with a series of pulses from lower to increasing voltage magnitudes;

#FIG. 2 is a block diagram view of a circuit for eFuse protection according to one embodiment of the present disclosure;

#As discussed herein, each signal may be designed as positive or negative logic, where negative logic can be indicated by a bar over the signal name or an “_B” following the name. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

#As used herein, VDD is representative of a first supply voltage useful to provide power to a control circuit that selects the eFuses to be programmed. In addition, as used herein, VSS is representative of a reference voltage. Furthermore, as used herein, PVDD is representative of a second supply voltage, in particular, useful in programming an eFuse.

#According to the embodiments of the present disclosure, protection circuitry is configured to disable the programming supply of the eFuses in a fuse array during ESD events and during power-up events. This advantageously eliminates the risk of false programming of the eFuses during any of these events. For ESD, a trigger signal is generated by an ESD network, wherein the ESD trigger signal is high during the ESD event and low during normal circuit operation. For power-up, a signal is derived from the supply voltage of a logic block that controls an eFuse address matrix.