Image sensing apparatus and image capturing system
AssigneeCanon Kabushiki Kaisha
InventorsAkira Okita, Satoshi Suzuki
Life of this patent
Estimating the term…
Abstract
An image sensing apparatus comprises a pixel and a driving unit, wherein the driving unit includes a buffer circuit including a first PMOS transistor and a first NMOS transistor, and letting V3 be a voltage supplied to a gate of the first NMOS transistor to supply a transfer signal for turning off the transfer MOS transistor to the transfer control line, V4 be a voltage supplied to a gate of the first PMOS transistor to supply a transfer signal for turning on the transfer MOS transistor to the transfer control line, Vthp1 be a threshold voltage of the first PMOS transistor, and Vthn1 be a threshold voltage of the first NMOS transistor, (V2+Vthn1)<V3<V1 and V2<V4<(V1+Vthp1) are satisfied.
Claims6
An image sensing apparatus comprising:
- a pixel;
- and
- a driving unit which drives the pixel,
- wherein the pixel includes a photoelectric conversion unit, a charge-voltage converter which converts a signal based on an electric charge accumulated by the photoelectric conversion unit into a voltage, and a transfer MOS transistor which transfers the electric charge accumulated by the photoelectric conversion unit to the charge-voltage converter,
- wherein the driving unit includes a buffer circuit configured to supply a transfer signal to a transfer control line connected to a gate of the transfer MOS transistor,
- wherein the buffer circuit includes
- a first PMOS transistor having a drain connected to the transfer control line, and a source supplied with a power supply voltage V1,
- a first NMOS transistor having a drain connected to the transfer control line and the drain of the first PMOS transistor, and a source supplied with a reference voltage V2 with a sign opposite to a sign of the power supply voltage V1,
- a second PMOS transistor having a drain connected to the source of the first PMOS transistor, and a source supplied with the power supply voltage V1, and
- a second NMOS transistor having a drain connected to the source of the first NMOS transistor, and a source supplied with the reference voltage V2,
- wherein V3 is a voltage supplied to a gate of the first NMOS transistor to supply a transfer signal for turning off the transfer MOS transistor to the transfer control line,
- wherein V4 is a voltage supplied to a gate of the first PMOS transistor to supply a transfer signal for turning on the transfer MOS transistor to the transfer control line,
- wherein Vthp1 is a threshold voltage of the first PMOS transistor,
- wherein Vthn1 is a threshold voltage of the first NMOS transistor,
- wherein V6 and V8 are voltages supplied to gates of the second PMOS transistor and the second NMOS transistor to supply a transfer signal for turning off the transfer MOS transistor to the transfer control line,
- wherein V5 and V7 are voltages supplied to gates of the second PMOS transistor and the second NMOS transistor to supply a transfer signal for turning on the transfer MOS transistor to the transfer control line,
- wherein Vthp2 is a threshold voltage of the second PMOS transistor,
- wherein Vthn2 is a threshold voltage of the second NMOS transistor, and
- wherein
- (V2+Vthn1)<V3<V1
- V2<V4<(V1+Vthp1)
- V2<V5<(V1+Vthp2)<V6
- and
- V7<(V2+Vthn2)<V8<V1.
Dependencies are inferred from the claim text.