US 8,009,172 B2 · Graphics processing unit with shared arithmetic logic unit

Abstract

This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

Claims30

Dependent claims

A method comprising:

receiving image data for an image within a graphics processing unit (GPU) pipeline that processes the image data within multiple stages using a same shared arithmetic logic unit and at least one other arithmetic logic unit;
and
processing the image data within the GPU pipeline using the same shared arithmetic logic unit for an attribute gradient setup stage, which computes gradients of attributes associated with primitives for the image data, and for an attribute interpolator stage, which interpolates the attributes over pixels within the primitives based on the gradients, other stages of the multiple stages using the at least one other arithmetic logic unit, wherein the attribute gradient setup stage and the attribute interpolator stage follow a rasterizer stage, the rasterizer stage converts primitives into pixels using vertex coordinate data.

A device comprising:

means for receiving image data for an image within a graphics processing unit (GPU) pipeline, the GPU pipeline having multiple stages and using a same shared arithmetic logic unit and at least one other arithmetic logic unit;
means for processing the image data in an attribute gradient setup stage, which computes gradients of attributes associated with primitives for the image data, using the same shared arithmetic logic unit;
and
means for processing the image data in an attribute interpolator stage, which interpolates the attributes over pixels within the primitives based on the gradients, using the same shared arithmetic logic unit, other stages of the multiple stages using the at least one other arithmetic logic unit, wherein the attribute gradient setup stage and the attribute interpolator stage follow a rasterizer stage, the rasterizer stage converts primitives into pixels using vertex coordinate data.

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Dependencies are inferred from the claim text.

Graphics processing unit with shared arithmetic logic unit

Life of this patent

Graphics processing unit with shared arithmetic logic unit

Life of this patent

Abstract

Claims30