Semiconductor display device and method of driving a semiconductor display device

A semiconductor display device comprising:

• a pixel portion having a plurality of pixels;
• a source signal line driver circuit;
• and
• a frame rate conversion portion, wherein:
• the plurality of pixels each has:
• a switching element;
• a pixel electrode;
• and an opposing electrode;
• the frame rate conversion portion has a data format portion and one RAM, or a plurality of RAMs;
• digital image signals are written into the one RAM, or into one of the plurality of RAMs;
• the digital image signals written into the one RAM, or into one of the plurality of RAMs, are each read out twice;
• the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion;
• one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted;
• the digital image signals output from the data format portion are both converted into analog signals in a D/A converter circuit, and then input to the source signal line driver circuit;
• two display signals are generated by the source signal line driver circuit;
• the two display signals have mutually inverted polarities;
• the two generated display signals are input to the pixel electrodes through the switching elements;
• and
• a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.

A semiconductor display device comprising:

• a pixel portion having a plurality of pixels;
• a source signal line driver circuit;
• and
• a frame rate conversion portion, wherein:
• the plurality of pixels each has:
• a switching element;
• a pixel electrode;
• and an opposing electrode;
• the frame rate conversion portion has a data format portion and one RAM, or a plurality of RAMs;
• digital image signals are written into the one RAM, or into one of the plurality of RAMs;
• the digital image signals written into the one RAM, or into one of the plurality of RAMs, are each read out twice;
• the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion;
• one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted;
• the digital image signals output from the data format portion are input to the source signal line driver circuit;
• two display signals are generated by the source signal line driver circuit;
• the two display signals have mutually inverted polarities;
• the two generated display signals are input to the pixel electrodes through the switching elements;
• within each frame period, all of the display signals input to the pixel electrodes have the same polarity, with an electric potential of the opposing electrode as a reference;
• and
• a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.

A semiconductor display device comprising:

• a pixel portion having a plurality of pixels;
• a source signal line driver circuit;
• and
• a frame rate conversion portion, wherein:
• the plurality of pixels each has:
• a switching element;
• a pixel electrode;
• and an opposing electrode;
• the frame rate conversion portion has a data format portion and one RAM, or a plurality of RAMs;
• digital image signals are written into the one RAM, or into one of the plurality of RAMs;
• the digital image signals written into the one RAM, or into one of the plurality of RAMs, are each read out twice;
• the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion;
• one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted;
• the digital image signals output from the data format portion are both converted into analog signals in a D/A converter circuit, and then input to the source signal line driver circuit;
• two display signals are generated by the source signal line driver circuit;
• the two display signals have mutually inverted polarities;
• the two generated display signals are input to the pixel electrodes through the switching elements;
• within each frame period, all of the display signals input to the pixel electrodes have the same polarity, with an electric potential of the opposing electrode as a reference;
• and
• a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.

A semiconductor display device comprising:

• a pixel portion having a plurality of pixels;
• a source signal line driver circuit;
• a plurality of source signal lines;
• and
• a frame rate conversion portion, wherein:
• the plurality of pixels each has:
• a switching element;
• a pixel electrode;
• and an opposing electrode;
• the frame rate conversion portion has a data format portion and one RAM, or a plurality of RAMs;
• digital image signals are written into the one RAM, or into one of the plurality of RAMs;
• the digital image signals written into the one RAM, or into one of the plurality of RAMs, are each read out twice;
• the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion;
• one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted;
• the digital image signals output from the data format portion are input to the source signal line driver circuit;
• two display signals are generated by the source signal line driver circuit;
• the two display signals have mutually inverted polarities;
• the two generated display signals are input to the pixel electrodes through the plurality of source signal lines and through the switching elements;
• within each frame period:
• display signals having mutually inverse polarities, with an electric potential of the opposing electrode as a reference, are input to source signal lines adjacent to the plurality of source signal lines;
• and the display signals input to the plurality of source signal lines always have the same polarity, with the electric potential of the opposing electrode as a reference;
• and
• a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.

A semiconductor display device comprising:

• a pixel portion having a plurality of pixels;
• a source signal line driver circuit;
• a plurality of source signal lines;
• and
• a frame rate conversion portion, wherein:
• the plurality of pixels each has:
• a switching element;
• a pixel electrode;
• and an opposing electrode;
• the frame rate conversion portion has a data format portion and one RAM, or a plurality of RAMs;
• digital image signals are written into the one RAM, or into one of the plurality of RAMS;
• the digital image signals written into the one RAM, or into one of the plurality of RAMs, are each read out twice;
• the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion;
• one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted;
• the digital image signals output from the data format portion are both converted into analog signals in a D/A converter circuit and then input to the source signal line driver circuit;
• two display signals are generated by the source signal line driver circuit;
• the two display signals have mutually inverted polarities;
• the two generated display signals are input to the pixel electrodes through the plurality of source signal lines and through the switching elements;
• within each frame period:
• display signals having mutually inverse polarities, with an electric potential of the opposing electrode as a reference, are input to source signal lines adjacent to the plurality of source signal lines;
• and the display signals input to the plurality of source signal lines always have the same polarity, with the electric potential of the opposing electrode as a reference;
• and
• a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.

A semiconductor display device comprising:

• a pixel portion having a plurality of pixels;
• a source signal line driver circuit;
• a plurality of source signal lines;
• and
• a frame rate conversion portion, wherein:
• the plurality of pixels each has:
• a switching element;
• a pixel electrode;
• and an opposing electrode;
• the frame rate conversion portion has a data format portion and one RAM, or a plurality of digital image signals are written into the one RAM, or into one of the plurality of RAMs;
• the digital image signals written into the one RAM, or into one of the plurality of RAMs, are each read out twice;
• the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion;
• one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted;
• the digital image signals output from the data format portion are input to the source signal line driver circuit;
• two display signals are generated by the source signal line driver circuit;
• the two display signals have mutually inverted polarities;
• the two generated display signals are input to the pixel electrodes through the plurality of source signal lines and through the switching elements;
• within each line period, the display signals input to all of the plurality of source signal lines always have the same polarity, with an electric potential of the opposing electrode as a reference;
• the polarities of the display signals input to the plurality of resource source signal lines are mutually inverted in adjacent line periods, with the electric potential of the opposing electrode as a reference;
• and
• a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.

A semiconductor display device comprising:

• a pixel portion having a plurality of pixels;
• a source signal line driver circuit;
• and
• a frame rate conversion portion, wherein:
• the plurality of pixels each has:
• a switching element;
• a pixel electrode;
• and an opposing electrode;
• the frame rate conversion portion has a data format portion and one RAM, or a plurality of RAMs;
• digital image signals are written into the one RAM, or into one of the plurality of RAMs;
• the digital image signals written into the one RAM, or into one of the plurality of RAMS, are each read out twice;
• the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion;
• one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted;
• the digital image signals output from the data format portion are both converted into analog signals in a D/A converter circuit, and then input to the source signal line driver circuit;
• two display signals are generated by the source signal line driver circuit;
• the two display signals have mutually inverted polarities;
• the two generated display signals are input to the pixel electrodes through the switching elements;
• within each line period, the display signals input to all of the plurality of source signal lines always have the same polarity, with an electric potential of the opposing electrode as a reference;
• the polarities of the display signals input to the plurality of source signal lines are mutually inverted in adjacent line periods, with the electric potential of the opposing electrode as a reference;
• and
• a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.

A semiconductor display device comprising:

• a pixel portion having a plurality of pixels;
• a source signal line driver circuit;
• a plurality of source signal lines;
• and
• a frame rate conversion portion, wherein:
• the plurality of pixels each has:
• a switching element;
• a pixel electrode;
• and an opposing electrode;
• the frame rate conversion portion has a data format portion and one RAM, or a plurality of RAMs;
• digital image signals are written into the one RAM, or into one of the plurality of RAMs;
• the digital image signals written into the one RAM, or into one of the plurality of RAMs, are each read out twice;
• the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion;
• one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted;
• the digital image signals output from the data format portion are input to the source signal line driver circuit;
• two display signals are generated by the source signal line driver circuit;
• the two display signals have mutually inverted polarities;
• the two generated display signals are input to the pixel electrodes through the switching elements;
• display signals having mutually inverse polarities, with an electric potential of the opposing electrode as a reference, are input to source signal lines adjacent to the plurality of source signal lines within each frame period;
• the polarities of the display signals input to the plurality of source signal lines are mutually inverted in adjacent line periods, with the electric potential of the opposing electrode as a reference;
• and
• a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.

A semiconductor display device comprising:

• a pixel portion having a plurality of pixels;
• a source signal line driver circuit;
• a plurality of source signal lines;
• and
• a frame rate conversion portion, wherein:
• the plurality of pixels each has:
• a switching element;
• a pixel electrode;
• and an opposing electrode;
• the frame rate conversion portion has a data format portion and one RAM, or a plurality of RAMs;
• digital image signals are written into the one RAM, or into one of the plurality of RAMs;
• the digital image signals written into the one RAM, or into one of the plurality of RAMs, are each read out twice;
• the digital image signals which are read out twice from the one RAM or from one of the plurality of RAMs are input to the data format portion;
• one of the digital image signals undergoes data processing in the data format portion so that polarity of the one of the digital image signals is inverted;
• the digital image signals output from the data format portion are both converted into analog signals in a D/A converter circuit, and then input to the source signal line driver circuit;
• two display signals are generated by the source signal line driver circuit;
• the two display signals have mutually inverted polarities;
• the two generated display signals are input to the pixel electrodes through the switching elements;
• display signals having mutually inverse polarities, with an electric potential of the opposing electrode as a reference, are input to source signal lines adjacent to the plurality of source signal lines within each frame period;
• the polarities of the display signals input to the plurality of source signal lines are mutually inverted in adjacent line periods, with the electric potential of the opposing electrode as a reference;
• and
• a period in which one digital image signal is written into the one RAM or is written into one of the plurality of RAMs is longer than a period during which the written in digital image signal is read out a first time, and longer than a period during which the written in digital image signal is read out a second time.