Method and device for encoding a bit sequence

Method for forming a sequence of bits from first and second encoded bit planes, wherein said method comprises using a processor for executing the steps of

• decoding the first bit planes resulting in a first sequence of unary representations,
• decoding the second bit planes resulting in a second sequence of unary representations,
• using the first sequence for generating runs of Ones wherein, for each unary representation comprised in the first sequence, a run of Ones of corresponding length is generated,
• using the second sequence for generating runs of Zeroes wherein, for each unary representation comprised in the second sequence, a run of Zeroes of corresponding length is generated, and
• forming the sequence of bits by alternating the generated runs of Zeroes and the generated runs of Ones.

Device for encoding a bit sequence, said device comprises

• generating means for generating, for each run of Ones comprised in the bit sequence, a unary representations of the length of the respective run of Ones,
• said generating means being adapted for generating, for each run of Zeroes comprised in the bit sequence, a unary representation of the length of the respective run of Zeroes,
• concatenating means for generating a first sequence by concatenating the generated unary representations of lengths of runs of Ones,
• said concatenating means being adapted for generating a second sequence by concatenating the generated unary representations of lengths of runs of Zeroes and
• means for bit plane encoding the generated first and second sequence of unary representations.

Device for decoding a sequence of bits from first and second encoded bit planes, said device comprises

• decoding means for decoding the first bit planes resulting in a first sequence of unary representations,
• said decoding means being adapted for decoding the second bit planes resulting in a second sequence of unary representations
• generating means for using the first sequence for generating runs of Ones wherein, for each unary representation comprised in the first sequence, a run of Ones of corresponding length is generated,
• said generating means being adapted for using the second sequence for generating runs of Zeroes wherein, for each unary representation comprised in the second sequence, a run of Zeroes of corresponding length is generated, and
• means for forming the sequence of bits by alternating the generated runs of Zeroes and the generated runs of Ones.