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US 8,008,963 B2Granted
Analog switch
AssigneeHitachi, Ltd.
InventorsMasahito Sonehara, Yoichiro Kobayashi
Life of this patent
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Abstract
An analog switch having a low capacitance is achieved. Potentials of input/output terminals of the analog switch and a well potential and a gate potential of an NMOS switching device are operated in synchronization via level shift buffers, thereby cancelling parasitic capacitances present between these elements.
Claims17
An analog switch comprising:
- a MOSFET having a source, a drain, a gate, and a well as terminals;
- a switching input terminal connected to one of the source and the drain, and a switching output terminal connected to the other of the source and the drain;
- a switching control terminal connected to the gate directly or indirectly, and to which a potential for maintaining an electrical conduction between the switching input terminal and the switching output terminal to an ON state or an OFF state is applied;
- and
- a level shift buffer which has an input terminal connected to the switching output terminal directly or indirectly and an output terminal connected to at least one of the gate and the well, and which causes at least one of a gate potential and a well potential to follow a potential of the switching output terminal.
2 more elements
Dependencies are inferred from the claim text.