Electronic device and method of correcting clock signal deviations in an electronic device

A digital electronic device, comprising:

• digital clock deviation detecting means for detecting a deviation of a first clock signal of the electronic device and/or the duty cycle of the first clock signal, said digital clock deviation detecting means configured for:
• measuring the duty cycle of the first clock signal at edges of a second clock signal, wherein the second clock signal is slower than the first clock signal;
• computing expected values of the duty cycle of the first clock signal;
• comparing the measured and the computed values of the duty cycle of the first clock signal;
• and
• incrementing a first counter with a first or second increment according to the comparison of the measured and computed values of the duty cycle of the first clock signal;
• and
• digital clock correcting means for correcting the first clock signal and/or the duty cycle of the first clock signal if the clock deviation detecting means has detected a deviation of the first clock signal and/or the duty cycle of the first clock signal;
• wherein said clock correcting means comprises at least a first and second compensation path for compensating the deviations in the first clock signal and/or the duty cycle thereof when the first clock signal passes through the first or second path;
• wherein the first compensation path does not include compensation and is selected if the clock deviation detecting means has not detected a deviation of the first clock signal;
• wherein the second compensation path includes a first compensation and is selected if the clock deviation detecting means has detected the deviation of the first clock signal.