Back to results
US 8,008,957 B2Granted
Inverting zipper repeater circuit
OwnerRobert Paul Masleidinventor
Life of this patent
Estimating the term…
Abstract
Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described.
Claims14
A method comprising:
- delaying an input signal by using a first delay chain of inverters;
- in response to a rising edge of the input signal, controlling an output to provide a first low logic level before a falling edge of the input signal;
- in response to the falling edge of the input signal, controlling the output to provide a second logical level before the rising edge of the input signal;
- and
- maintaining logic level of the output between the rising edge and the falling edge of the input signal by using a second delay chain of inverters, providing an output signal to the output, wherein the output signal of the second delay chain of inverters is excluded from an input of the first delay chain of inverters.
2 more elements
A method comprising:
- delaying an input signal by using a first delay chain of inverters;
- in response to a rising edge of the input signal, activating and deactivating a first circuit element before a falling edge of the input signal to provide an output falling edge signal at an output terminal;
- in response to the falling edge of the input signal, activating and deactivating a second circuit element before the rising edge of the input signal to provide an output rising edge signal at the output terminal;
- between the rising edge and the falling edge, holding a state of the output terminal by using a second delay chain of inverters, coupled to the output terminal wherein the first delay chain of inverters shares an inverter with the second delay chain of inverters;
- and
- wherein the input of the first delay chain of inverters is excluded from the output terminal.
3 more elements
A method comprising:
- delaying an input signal by using a first delay chain of inverters;
- in response to a rising edge of the input signal, activating and deactivating a first circuit element before a falling edge of the input signal to provide an output falling edge signal at an output terminal;
- in response to the falling edge of the input signal, activating and deactivating a second circuit element before the rising edge of the input signal to provide an output rising edge signal at the output terminal;
- between the rising edge and the falling edge, maintaining a state of the output terminal by using a second delay chain of inverters, coupled to the output terminal wherein the first delay chain of inverters shares an inverter with the second delay chain of inverters;
- and
- wherein the input of the first delay chain of inverters is excluded from the output terminal.
3 more elements
Dependencies are inferred from the claim text.