Multi-phase signal generator and method
AssigneeMicron Technology, Inc.
InventorYantao Ma
Life of this patent
Estimating the term…
Abstract
Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock signals including those having 90, 180, 270 and 360 degrees phase difference with a first clock signal. One of the intermediate clock signals may be used as an enable signal to guide locking of all signals. For example, the 180 degree clock signal may be inverted and used as an enable signal to guide locking of the initial and 360 degree signals in a single phase adjustment procedure. The 0 and 360 degree signals may be delayed before their phase is compared to compensate for duty cycle error in the clock signals.
Claims32
A multi-phase periodic signal generator comprising:
- a plurality of delay elements including a first delay element, an intermediate delay element, and a third delay element, each of the first and second delay elements coupled such that an output of a respective delay element is coupled to an input of a next delay element, each of the respective delay elements configured to delay a signal applied to an input of the respective delay element and couple the delayed signal to the respective next delay element, the first delay element configured to receive a first periodic signal, the intermediate delay element configured to output an intermediate periodic signal, and the third delay element configured to output a third signal;
- a phase detector configured to receive the first signal, the third signal, and the intermediate signal, the phase detector configured to be enabled responsive to the intermediate signal and when enabled to provide a signal indicative of a phase difference between the first and third signals;
- a control signal generator configured to receive the signal indicative of the phase difference between the first and third signals and generate a control signal to adjust the delay of the plurality of delay elements such that the first, intermediate and third signals have a predetermined phase relationship;
- and
- a duty cycle distortion tolerance delay element configured to receive the first signal and the third signal, the duty cycle distortion tolerance delay element configured to delay the respective first and third signals and output the delayed first and third signals to the phase detector.
A memory device comprising:
- an input buffer configured to receive an input clock signal;
- a multi-phase periodic signal generator coupled to the input buffer, the multi-phase periodic signal generator comprising:
- a plurality of delay elements including a first delay element, an intermediate delay element, and a third delay element, each of the first and second delay elements coupled such that an output of a respective delay element is coupled to an input of a next delay element, each of the respective delay elements configured to delay a signal applied to an input of the respective delay element and couple the delayed signal to the respective next delay element, the first delay element configured to receive a first periodic signal based on the input clock signal, the intermediate delay element configured to output an intermediate periodic signal, and the third delay element configured to output a third signal;
- a phase detector configured to receive the first signal, the third signal, and the intermediate signal, the phase detector configured to be enabled responsive to the intermediate clock signal and when enabled to provide a signal indicative of a phase difference between the first and third signals;
- a control signal generator configured to receive the signal indicative of the phase difference between the first and third signals and generate a control signal to adjust the delay of the plurality of delay elements such that the first, intermediate and third signals have a predetermined phase relationship;
- a duty cycle distortion tolerance delay element configured to receive the first signal and the third signal, the duty cycle distortion tolerance delay element configured to delay the respective first and third signals and output the delayed first and third signals to the phase detector;
- and
- an array of memory cells, the array of memory cells coupled to receive the intermediate and third signals.
A method for generating a plurality of periodic signals including a first clock signal, an intermediate clock signal having a first phase relationship with the first clock signal, and final clock signal having a second phase relationship with the first clock signal, the method comprising:
- delaying the first signal a first delay amount to generate the intermediate clock signal;
- delaying the intermediate signal a second delay amount to generate the final signal;
- enabling a phase detector using the intermediate signal;
- delaying the first and final signals a compensation delay amount prior to measuring the phase difference between the first and final signals;
- measuring a phase difference between the first and final signals while the phase detector is enabled;
- and
- adjusting the first and second delay amounts based on the phase difference.
Dependencies are inferred from the claim text.