US 8,008,952 B2 · Buffer circuit having switch circuit capable of outputing two and more different high voltage potentials

Abstract

A buffer circuit outputs a low voltage and high voltages as opposed logic signals and a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages. The buffer includes a logic control circuit, a first MOS transistor provided between a power supply for feeding the first high voltage and an output terminal, the first MOS transistor including a gate receiving a control signal of the first high voltage level outputted from the logic control circuit, and a backgate receiving the first high voltage, a second MOS transistor provided between a power supply for feeding the second high voltage and the output terminal, the second MOS transistor including a gate receiving a control signal of the second high voltage level outputted from the logic control circuit, and a backgate receiving the second high voltage, and a first switch circuit provided between the first MOS transistor and the output terminal and controlled ON/OFF state thereof by the control signal of the second high voltage level.

Claims12

Dependent claims

A buffer circuit for outputting low and high voltages as opposed logic signals and capable of outputting a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages, the buffer circuit comprising:

a logic control circuit;
a first metal oxide semiconductor (MOS) transistor provided between a power supply for feeding the first high voltage and an output terminal, the first MOS transistor including a gate receiving a control signal of the first high voltage outputted from the logic control circuit, and a backgate receiving the first high voltage;
a second MOS transistor provided between a power supply for feeding the second high voltage and the output terminal, the second MOS transistor including a gate receiving a control signal of the second high voltage outputted from the logic control circuit, and a backgate receiving the second high voltage;
and
a switch circuit provided between the first MOS transistor and the output terminal and an ON/OFF state thereof being controlled by the control signal of the second high voltage level.

2 more elements

A buffer circuit, comprising:

a first power source node receiving a first power source potential;
a second power source node receiving a second power source potential lower than the first power source potential;
a third power source node receiving a third power source potential lower than the second power source potential;
a first transistor of a first conductive type coupled between the second power source node and a first node, and including a control gate controlled by the second power source potential and a back gate receiving the second power source potential;
a second transistor of the first conductive type coupled between the first power source node and an output node;
a third transistor of a second conductive type coupled between the third power source node and the output node;
and
a fourth transistor of the first conductive type coupled between the first node and the output node, and including a control gate controlled by the first power source potential and a back gate receiving the first power source potential.

5 more elements

Dependencies are inferred from the claim text.

Buffer circuit having switch circuit capable of outputing two and more different high voltage potentials

Life of this patent

Buffer circuit having switch circuit capable of outputing two and more different high voltage potentials

Life of this patent

Abstract

Claims12