Peak voltage detector circuit and binarizing circuit including the same circuit

A peak voltage detector circuit for detecting a positive peak voltage of an input voltage comprising:

• a comparator having a noninversion input terminal and an inversion input terminal, wherein the input voltage is input into the noninversion input terminal of the comparator;
• a first clock signal generating circuit for generating a first clock signal;
• a second clock signal generating circuit for generating a second clock signal;
• a counter circuit for adding a counter value in synchronization with the first clock signal, when an output signal output from the comparator is high, wherein the counter circuit subtracts the counter value in synchronization with the second clock signal;
• and
• a digital-analog conversion circuit for outputting an output voltage corresponding to the counter value of the counter circuit, wherein the output voltage of the digital-analog conversion circuit is input into the inversion input terminal of the comparator, wherein
• the first clock signal has a wave period shorter than that of the second clock signal.

A binarizing circuit for converting an input voltage having an alternating waveform into a digital signal, the binarizing circuit comprising:

• a first peak voltage detector circuit for detecting a positive peak voltage of an input voltage;
• a second peak voltage detector circuit for detecting a negative peak voltage of an input voltage;
• and
• a determination circuit for providing a threshold voltage based on the positive peak voltage provided by the first peak voltage detector circuit and the negative peak voltage provided by the second peak voltage detector circuit, wherein
• the first peak voltage detector circuit includes:
• a first comparator having a noninversion input terminal and an inversion input terminal, wherein the input voltage is input into the noninversion input terminal of the first comparator;
• a first clock signal generating circuit for generating a first clock signal;
• a second clock signal generating circuit for generating a second clock signal;
• a first counter circuit for adding a counter value in synchronization with the first clock signal, when an output signal output from the first comparator is high, wherein the first counter circuit subtracts the counter value in synchronization with the second clock signal;
• and
• a first digital-analog conversion circuit for outputting an output voltage corresponding to the counter value of the first counter circuit, wherein the output voltage of the first digital-analog conversion circuit is input into the inversion input terminal of the first comparator, and wherein the first clock signal has a wave period shorter than that of the second clock signal,
• the second peak voltage detector circuit includes:
• a second comparator having a noninversion input terminal and an inversion input terminal, wherein the input voltage is input into the inversion input terminal of the second comparator;
• a third clock signal generating circuit for generating a third clock signal;
• a fourth clock signal generating circuit for generating a fourth clock signal;
• a second counter circuit for subtracting a counter value in synchronization with the third clock signal, when an output signal output from the second comparator is high, wherein the second counter circuit adds the counter value in synchronization with the fourth clock signal;
• and
• a second digital-analog conversion circuit for outputting an output voltage corresponding to the counter value of the second counter circuit, wherein the output voltage of the second digital-analog conversion circuit is input into the noninversion input terminal of the second comparator, and wherein the third clock signal has a wave period shorter than that of the fourth clock signal, and
• the determination circuit determines the input voltage to be high or low based on the provided threshold voltage.