Semiconductor integrated circuit
AssigneeKabushiki Kaisha Toshiba
InventorMariko Iizuka
Life of this patent
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Abstract
A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.
Claims6
A semiconductor integrated circuit, comprising:
- a plurality of circuit units arranged therein;
- a first counter configured to detect a rising edge of a clock signal and generate a first signal having a multiplied cycle of the clock signal;
- a second counter configured to detect a falling edge of the clock signal and generate a second signal having a multiplied cycle of the clock signal;
- a first line for transferring the first signal;
- a second line for transferring the second signal;
- and
- a phase comparator connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units,
- the phase comparator being disposed on the first line and the second line, and plurality of the phase comparators being disposed between ends of the first line and the second line and the circuit units, wherein
- the wiring time constant of the first line and the wiring time constant of the second line are less than half of the cycles of the first signal and the second signal transferred on the first line and the second line.
A semiconductor integrated circuit, comprising:
- a plurality of circuit units arranged therein;
- a first counter configured to detect a rising edge of a clock signal and generate a first signal having a multiplied cycle of the clock signal;
- a second counter configured to detect a falling edge of the clock signal and generate a second signal having a multiplied cycle of the clock signal;
- a first line for transferring the first signal;
- a second line for transferring the second signal;
- and
- a phase comparator connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units,
- the phase comparator being disposed on the first line and the second line, and plurality of the phase comparators being disposed between ends of the first line and the second line and the circuit units,
- wherein the first inverter and the second inverter are disposed at positions so that the wiring time constant of the first line and the wiring time constant of the second line are equal, and
- the wiring time constant of the first line and the wiring time constant of the second line are less than half of the cycles of the first signal and the second signal transferred on the first line and the second line.
Dependencies are inferred from the claim text.