Semiconductor device
AssigneeHynix Semiconductor Inc.
InventorsTae-Sik Yun, Kang-Seol Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.
Claims9
A semiconductor device, comprising:
- a signal generating unit configured to generate a bandwidth selection signal for adjusting a data input/output bandwidth or generate a test mode selection signal for controlling an entry into a test mode in response to a signal inputted externally through a predetermined first pad;
- a reset unit configured to initialize an internal circuit in response to a signal inputted externally through a predetermined second pad;
- and
- a logic level fixing unit configured to pass the signal inputted through the predetermined second pad during a normal mode and output a fixed signal regardless of changes in the signal inputted through the predetermined second pad in response to the test mode selection signal.
A semiconductor device, comprising:
- a signal generating unit configured to generate a bandwidth selection signal for adjusting a data input/output bandwidth or generate a test mode selection signal for controlling an entry into a test mode in response to a plurality of signals inputted from the outside through a plurality of control signal input pads;
- a reset unit configured to initialize a plurality of internal circuits in response to a reset signal inputted externally through a reset signal input pad;
- and
- a logic level fixing unit configured to pass the reset signal as an output of the logic level fixing unit during a normal operation and output a fixed signal regardless of changes in the reset signal in response to the test mode selection signal.
Dependencies are inferred from the claim text.