Tester and a method for testing an integrated circuit

A method for testing an integrated circuit, the method comprises:

• providing a first signal to a first path that starts within the integrated circuit and ends at a first memory element that is followed by a first IO pad, and providing a second signal to a second path that starts within the integrated circuit and ends at a second memory element that is followed by a second IO pad;
• comparing between a first test result and a second test result, wherein the first test result represents a first state of the first memory element sampled a predefined period after a first provision of the first signal and the second test result represents a second state of the second memory element sampled the predefined period after a second provision of the second signal;
• altering the predefined period;
• and
• repeating the stages of providing, comparing and altering until detecting a time difference between a first path propagation period and a second path propagation period.

A method for testing an integrated circuit, the method comprises:

• providing a first signal to a first path that starts within the integrated circuit and ends at a first memory element that is followed by a first IO pad;
• providing a second signal to a second path that starts within the integrated circuit and ends at a second memory element that is followed by a second IO pad;
• sampling a first state of the first memory element and the first IO pad at a first predefined period after a first provision of the first signal to get a first test result;
• sampling a second state of the second memory element and the second IO pad at the first predefined period after a second provision of the second signal to get a second test result;
• comparing the first test result and the second test result by XORing the first test result with the second test result;
• altering the first predefined period to get a second predefined period;
• providing the first signal to the first path in response to altering the first predefined period;
• providing the second signal to the second path in response to altering the first predefined period;
• sampling a third state of the first memory element and the first IO pad at the second predefined period after a third provision of the first signal to get a third test result;
• sampling a fourth state of the second memory element and the second IO pad at the second predefined period after a fourth provision of the second signal to get a fourth test result;
• and
• comparing the third test result and the fourth test result by XORing the third test result with the fourth test result.